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PCIE_Brige_PCB PCB ECO 2022-11-20 21-07-23.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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PCIE_Brige_PCB PCB ECO 2022-11-20 22-34-30.LOG
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PCB初始化
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2022-11-21 00:10:13 +08:00 |
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PCIE_Brige_PCB PCB ECO 2022-11-20 23-38-56.LOG
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PCB初始化
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2022-11-21 00:10:13 +08:00 |
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PCIE_Brige_PCB PCB ECO 2022-11-20 23-43-40.LOG
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PCB初始化
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2022-11-21 00:10:13 +08:00 |
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PCIE_Brige_PCB PCB ECO 2022-11-21 10-57-13.LOG
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第一次布线完成
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2022-11-21 13:17:30 +08:00 |
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PCIE_Brige_PCB PCB ECO 2022-11-21 10-58-24.LOG
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第一次布线完成
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2022-11-21 13:17:30 +08:00 |
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PCIE_Brige_PCB PCB ECO 2022-11-21 13-08-17.LOG
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第一次布线完成
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2022-11-21 13:17:30 +08:00 |
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PCIE_Brige_PCB PCB ECO 2022-11-21 13-15-34.LOG
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第一次布线完成
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2022-11-21 13:17:30 +08:00 |
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PCIE_Brige_PCB PCB ECO 2022-11-21 13-30-46.LOG
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重新设置最小间距为6mil
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2022-11-21 17:10:20 +08:00 |
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PCIE_Brige_PCB PCB ECO 2022-11-21 13-33-11.LOG
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重新设置最小间距为6mil
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2022-11-21 17:10:20 +08:00 |
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PCIE_Brige_PCB PCB ECO 2022-11-21 13-34-11.LOG
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重新设置最小间距为6mil
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2022-11-21 17:10:20 +08:00 |
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PCIE_Brige_PCB PCB ECO 2022-11-21 13-36-46.LOG
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重新设置最小间距为6mil
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2022-11-21 17:10:20 +08:00 |
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PCIE_Brige_PCB PCB ECO 2022-11-22 17-24-45.LOG
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Test product V.01
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2022-11-22 17:46:08 +08:00 |
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Pcie_Brige_Borad PCB ECO 2022-11-18 18-19-02.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Borad PCB ECO 2022-11-18 18-20-20.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Borad PCB ECO 2022-11-18 18-33-07.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Borad PCB ECO 2022-11-18 23-10-09.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Borad PCB ECO 2022-11-18 23-21-17.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Borad PCB ECO 2022-11-18 23-34-52.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Borad PCB ECO 2022-11-19 15-43-16.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Borad PCB ECO 2022-11-19 16-11-44.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Borad PCB ECO 2022-11-19 16-21-55.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Borad PCB ECO 2022-11-19 22-24-23.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Borad PCB ECO 2022-11-19 22-51-01.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Borad PCB ECO 2022-11-19 22-53-37.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Borad PCB ECO 2022-11-19 22-57-44.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Borad PCB ECO 2022-11-19 22-58-22.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Borad PCB ECO 2022-11-19 23-11-24.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Borad PCB ECO 2022-11-19 23-18-22.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Borad PCB ECO 2022-11-20 13-27-14.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Borad PCB ECO 2022-11-20 14-15-27.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Borad PCB ECO 2022-11-20 14-57-53.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Borad PCB ECO 2022-11-20 15-01-42.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Cfg SCH ECO 2022-11-18 18-20-11.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Cfg SCH ECO 2022-11-18 23-10-20.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Cfg SCH ECO 2022-11-19 22-56-27.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Cfg SCH ECO 2022-11-19 23-11-48.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Cfg SCH ECO 2022-11-20 13-53-57.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Cfg SCH ECO 2022-11-20 14-13-26.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Cfg SCH ECO 2022-11-20 22-28-29.LOG
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PCB初始化
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2022-11-21 00:10:13 +08:00 |
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Pcie_Brige_Cfg SCH ECO 2022-11-20 22-29-12.LOG
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PCB初始化
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2022-11-21 00:10:13 +08:00 |
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Pcie_Brige_Cfg SCH ECO 2022-11-20 22-29-33.LOG
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PCB初始化
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2022-11-21 00:10:13 +08:00 |
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Pcie_Brige_Cfg SCH ECO 2022-11-20 22-32-21.LOG
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PCB初始化
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2022-11-21 00:10:13 +08:00 |
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Pcie_Brige_Cfg SCH ECO 2022-11-20 23-35-28.LOG
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PCB初始化
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2022-11-21 00:10:13 +08:00 |
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Pcie_Brige_Cfg SCH ECO 2022-11-21 14-34-39.LOG
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重新设置最小间距为6mil
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2022-11-21 17:10:20 +08:00 |
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Pcie_Brige_Core SCH ECO 2022-11-18 16-59-40.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Core SCH ECO 2022-11-18 17-01-33.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Core SCH ECO 2022-11-18 18-20-11.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Core SCH ECO 2022-11-20 13-53-57.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Core SCH ECO 2022-11-20 14-13-26.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_Core SCH ECO 2022-11-20 22-29-12.LOG
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PCB初始化
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2022-11-21 00:10:13 +08:00 |
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Pcie_Brige_Core SCH ECO 2022-11-20 22-29-33.LOG
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PCB初始化
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2022-11-21 00:10:13 +08:00 |
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Pcie_Brige_pwr SCH ECO 2022-11-18 18-20-11.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_pwr SCH ECO 2022-11-20 13-53-57.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_pwr SCH ECO 2022-11-20 14-13-26.LOG
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first commit
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2022-11-20 21:10:53 +08:00 |
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Pcie_Brige_pwr SCH ECO 2022-11-20 22-29-12.LOG
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PCB初始化
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2022-11-21 00:10:13 +08:00 |
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Pcie_Brige_pwr SCH ECO 2022-11-20 22-29-33.LOG
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PCB初始化
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2022-11-21 00:10:13 +08:00 |
