Pcie_brige_test/Project Logs for Pcie_Brige.../Pcie_Brige_Borad PCB ECO 20...

13 lines
383 B
Plaintext

Added Net: Name=GND
Added Net: Name=PCIE_SW_ADDH_3V3
Added Net: Name=PCIE_SW_AVDD_1V0
Added Net: Name=PCIE_SW_CVDDR_3V3
Added Net: Name=PCIE_SW_VDDC_1V0
Added Net: Name=PCIE_SW_VDDR_3V3
Added Class: Name=Pcie_Brige_Cfg
Added Class: Name=Pcie_Brige_Core
Added Class: Name=Pcie_Brige_pwr
Added Room: Name=Pcie_Brige_Cfg
Added Room: Name=Pcie_Brige_Core
Added Room: Name=Pcie_Brige_pwr