Pcie_brige_test/Project Logs for Pcie_Brige.../Pcie_Brige_Borad PCB ECO 20...

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517 B
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Added Pin To Net: NetName=PCIE_SW_VDDR_3V3 Pin=U38-D14
Added Pin To Net: NetName=DB0 Pin=U38-N1
Added Net: Name=DB0
Added Net: Name=DB1
Added Pin To Net: NetName=DB2 Pin=U38-K3
Added Net: Name=DB2
Added Pin To Net: NetName=DB3 Pin=U38-F1
Added Net: Name=DB3
Added Pin To Net: NetName=DB4 Pin=U38-F3
Added Net: Name=DB4
Added Pin To Net: NetName=PORT_SEL_2 Pin=U38-H2
Added Net: Name=PORT_SEL_2
Added Pin To Net: NetName=PORT_SEL_3 Pin=U38-G2
Added Pin To Net: NetName=PORT_SEL_3 Pin=U38-G2
Added Net: Name=PORT_SEL_3