重新设置最小间距为6mil

2022-11-21 17:10:20 +08:00 · 2022-11-21 17:10:20 +08:00 · 7f915b5b60
--- a/History/PCIE_Brige_PCB.~(30).PcbDoc.Zip
+++ b/History/PCIE_Brige_PCB.~(30).PcbDoc.Zip
--- a/History/PCIE_Brige_PCB.~(31).PcbDoc.Zip
+++ b/History/PCIE_Brige_PCB.~(31).PcbDoc.Zip
--- a/History/PCIE_Brige_PCB.~(32).PcbDoc.Zip
+++ b/History/PCIE_Brige_PCB.~(32).PcbDoc.Zip
--- a/History/PCIE_Brige_PCB.~(33).PcbDoc.Zip
+++ b/History/PCIE_Brige_PCB.~(33).PcbDoc.Zip
--- a/History/PCIE_Brige_PCB.~(34).PcbDoc.Zip
+++ b/History/PCIE_Brige_PCB.~(34).PcbDoc.Zip
--- a/History/Pcie_Brige_Cfg.~(34).SchDoc.Zip
+++ b/History/Pcie_Brige_Cfg.~(34).SchDoc.Zip
--- a/History/Pcie_Brige_Cfg.~(35).SchDoc.Zip
+++ b/History/Pcie_Brige_Cfg.~(35).SchDoc.Zip
--- a/History/Pcie_Brige_Core.~(34).SchDoc.Zip
+++ b/History/Pcie_Brige_Core.~(34).SchDoc.Zip
--- a/History/Pcie_Brige_pwr.~(18).SchDoc.Zip
+++ b/History/Pcie_Brige_pwr.~(18).SchDoc.Zip
--- a/History/Pcie_Brige_pwr.~(19).SchDoc.Zip
+++ b/History/Pcie_Brige_pwr.~(19).SchDoc.Zip
--- a/History/Pcie_Brige_pwr.~(20).SchDoc.Zip
+++ b/History/Pcie_Brige_pwr.~(20).SchDoc.Zip
--- a/History/Pcie_Brige_pwr.~(21).SchDoc.Zip
+++ b/History/Pcie_Brige_pwr.~(21).SchDoc.Zip
--- a/History/Pcie_Brige_pwr.~(22).SchDoc.Zip
+++ b/History/Pcie_Brige_pwr.~(22).SchDoc.Zip
--- a/History/Pcie_Brige_pwr.~(23).SchDoc.Zip
+++ b/History/Pcie_Brige_pwr.~(23).SchDoc.Zip
--- a/PCIE_Brige_PCB.PcbDoc
+++ b/PCIE_Brige_PCB.PcbDoc
--- a/Pcie_Brige_Cfg.SchDoc
+++ b/Pcie_Brige_Cfg.SchDoc
--- a/Pcie_Brige_Core.SchDoc
+++ b/Pcie_Brige_Core.SchDoc
--- a/Pcie_Brige_pwr.SchDoc
+++ b/Pcie_Brige_pwr.SchDoc
--- a/Pcie_Brige_Test/PCIE_Brige_PCB
+++ b/Pcie_Brige_Test/PCIE_Brige_PCB
@ -0,0 +1,13 @@
+Removed Pin From Net: NetName=PCIE_SW_VDDC_1V0 Pin=P28-1
+Removed Pin From Net: NetName=PCIE_SW_VDDC_1V0 Pin=P28-2
+Removed Pin From Net: NetName=PCIE_SW_AVDD_1V0 Pin=P28-3
+Removed Pin From Net: NetName=PCIE_SW_VDDR_3V3 Pin=P28-4
+Removed Pin From Net: NetName=PCIE_SW_CVDDR_3V3 Pin=P28-5
+Removed Pin From Net: NetName=PCIE_SW_ADDH_3V3 Pin=P28-6
+Added Pin To Net: NetName=PCIE_SW_AVDD_1V0 Pin=P28-1
+Added Pin To Net: NetName=PCIE_SW_VDDR_3V3 Pin=P28-2
+Added Pin To Net: NetName=PCIE_SW_ADDH_3V3 Pin=P28-3
+Added Pin To Net: NetName=PCIE_SW_CVDDR_3V3 Pin=P28-4
+Added Pin To Net: NetName=PCIE_SW_VDDC_1V0 Pin=P28-5
+Added Pin To Net: NetName=PCIE_SW_VDDC_1V0 Pin=P28-6
+Added Pin To Net: NetName=PCIE_SW_VDDR_3V3 Pin=U1-D14
--- a/Pcie_Brige_Test/PCIE_Brige_PCB
+++ b/Pcie_Brige_Test/PCIE_Brige_PCB
@ -0,0 +1,5 @@
+Removed Pin From Net: NetName=PCIE_SW_AVDD_1V0 Pin=P28-1
+Removed Pin From Net: NetName=PCIE_SW_VDDR_3V3 Pin=P28-2
+Added Pin To Net: NetName=PCIE_SW_VDDR_3V3 Pin=P28-1
+Added Pin To Net: NetName=PCIE_SW_AVDD_1V0 Pin=P28-2
+Added Pin To Net: NetName=REFCLKO1_N Pin=U1-D14
--- a/Pcie_Brige_Test/PCIE_Brige_PCB
+++ b/Pcie_Brige_Test/PCIE_Brige_PCB
@ -0,0 +1,7 @@
+Removed Pin From Net: NetName=PCIE_SW_VDDR_3V3 Pin=P28-1
+Removed Pin From Net: NetName=PCIE_SW_AVDD_1V0 Pin=P28-2
+Removed Pin From Net: NetName=PCIE_SW_ADDH_3V3 Pin=P28-3
+Added Pin To Net: NetName=PCIE_SW_ADDH_3V3 Pin=P28-1
+Added Pin To Net: NetName=PCIE_SW_VDDR_3V3 Pin=P28-2
+Added Pin To Net: NetName=PCIE_SW_AVDD_1V0 Pin=P28-3
+Added Pin To Net: NetName=PCIE_SW_VDDR_3V3 Pin=U1-D14
--- a/Pcie_Brige_Test/PCIE_Brige_PCB
+++ b/Pcie_Brige_Test/PCIE_Brige_PCB
@ -0,0 +1 @@
+Added Pin To Net: NetName=REFCLKO1_N Pin=U1-D14
--- a/Pcie_Brige_Test/Pcie_Brige_Cfg
+++ b/Pcie_Brige_Test/Pcie_Brige_Cfg
--- a/__Previews/Pcie_Brige_Cfg.SchDocPreview
+++ b/__Previews/Pcie_Brige_Cfg.SchDocPreview
--- a/__Previews/Pcie_Brige_pwr.SchDocPreview
+++ b/__Previews/Pcie_Brige_pwr.SchDocPreview
				`@ -0,0 +1 @@`
				`Added Pin To Net: NetName=REFCLKO1_N Pin=U1-D14`