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Pcie_brige_test
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Test product V.01

master
邱棚 2022-11-22 17:46:08 +08:00
parent 676086060d
commit 975b94d138
95 changed files with 76164 additions and 395 deletions
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@ -31,7 +31,7 @@ ReportSuppressedErrorsInMessages=0
FSMCodingStyle=eFMSDropDownList_OneProcess
FSMEncodingStyle=eFMSDropDownList_OneHot
IsProjectConflictPreventionWarningsEnabled=0
OutputPath=
OutputPath=Project Outputs for Pcie_Brige_Test
LogFolderPath=
ManagedProjectGUID=
IncludeDesignInRelease=0
@ -148,6 +148,102 @@ DItemRevisionGUID=
GenerateClassCluster=0
DocumentUniqueId=DFNNDBII
[GeneratedDocument1]
DocumentPath=Project Outputs for Pcie_Brige_Test\Design Rule Check - PCIE_Brige_PCB.html
DItemRevisionGUID=
[GeneratedDocument2]
DocumentPath=Project Outputs for Pcie_Brige_Test\Fabrication Testpoint Report for PCIE_Brige_PCB.ipc
DItemRevisionGUID=
[GeneratedDocument3]
DocumentPath=Project Outputs for Pcie_Brige_Test\Fabrication Testpoint Report for PCIE_Brige_PCB.txt
DItemRevisionGUID=
[GeneratedDocument4]
DocumentPath=Project Outputs for Pcie_Brige_Test\PCIE_Brige_PCB.DRR
DItemRevisionGUID=
[GeneratedDocument5]
DocumentPath=Project Outputs for Pcie_Brige_Test\PCIE_Brige_PCB.EXTREP
DItemRevisionGUID=
[GeneratedDocument6]
DocumentPath=Project Outputs for Pcie_Brige_Test\PCIE_Brige_PCB.GBL
DItemRevisionGUID=
[GeneratedDocument7]
DocumentPath=Project Outputs for Pcie_Brige_Test\PCIE_Brige_PCB.GBO
DItemRevisionGUID=
[GeneratedDocument8]
DocumentPath=Project Outputs for Pcie_Brige_Test\PCIE_Brige_PCB.GBP
DItemRevisionGUID=
[GeneratedDocument9]
DocumentPath=Project Outputs for Pcie_Brige_Test\PCIE_Brige_PCB.GBS
DItemRevisionGUID=
[GeneratedDocument10]
DocumentPath=Project Outputs for Pcie_Brige_Test\PCIE_Brige_PCB.GD1
DItemRevisionGUID=
[GeneratedDocument11]
DocumentPath=Project Outputs for Pcie_Brige_Test\PCIE_Brige_PCB.GG1
DItemRevisionGUID=
[GeneratedDocument12]
DocumentPath=Project Outputs for Pcie_Brige_Test\PCIE_Brige_PCB.GM1
DItemRevisionGUID=
[GeneratedDocument13]
DocumentPath=Project Outputs for Pcie_Brige_Test\PCIE_Brige_PCB.GP1
DItemRevisionGUID=
[GeneratedDocument14]
DocumentPath=Project Outputs for Pcie_Brige_Test\PCIE_Brige_PCB.GP2
DItemRevisionGUID=
[GeneratedDocument15]
DocumentPath=Project Outputs for Pcie_Brige_Test\PCIE_Brige_PCB.GTL
DItemRevisionGUID=
[GeneratedDocument16]
DocumentPath=Project Outputs for Pcie_Brige_Test\PCIE_Brige_PCB.GTO
DItemRevisionGUID=
[GeneratedDocument17]
DocumentPath=Project Outputs for Pcie_Brige_Test\PCIE_Brige_PCB.GTP
DItemRevisionGUID=
[GeneratedDocument18]
DocumentPath=Project Outputs for Pcie_Brige_Test\PCIE_Brige_PCB.GTS
DItemRevisionGUID=
[GeneratedDocument19]
DocumentPath=Project Outputs for Pcie_Brige_Test\PCIE_Brige_PCB.LDP
DItemRevisionGUID=
[GeneratedDocument20]
DocumentPath=Project Outputs for Pcie_Brige_Test\PCIE_Brige_PCB.REP
DItemRevisionGUID=
[GeneratedDocument21]
DocumentPath=Project Outputs for Pcie_Brige_Test\PCIE_Brige_PCB.RUL
DItemRevisionGUID=
[GeneratedDocument22]
DocumentPath=Project Outputs for Pcie_Brige_Test\PCIE_Brige_PCB.TXT
DItemRevisionGUID=
[GeneratedDocument23]
DocumentPath=Project Outputs for Pcie_Brige_Test\Pick Place for PCIE_Brige_PCB.csv
DItemRevisionGUID=
[GeneratedDocument24]
DocumentPath=Project Outputs for Pcie_Brige_Test\Pick Place for PCIE_Brige_PCB.txt
DItemRevisionGUID=
[Configuration1]
Name=Sources
ParameterCount=0
@ -158,6 +254,45 @@ OutputJobsCount=0
ContentTypeGUID=CB6F2064-E317-11DF-B822-12313F0024A2
ConfigurationType=Source
[Generic_SmartPDF]
AutoOpenFile=-1
AutoOpenOutJob=-1
[Generic_SmartPDFSettings]
ProjectMode=-1
ZoomPrecision=50
AddNetsInformation=0
AddNetPins=-1
AddNetNetLabels=-1
AddNetPorts=-1
ShowComponentParameters=-1
GlobalBookmarks=0
ExportBOM=0
TemplateFilename=C:\Users\Public\Documents\Altium\AD22\Templates\BOM Template Single Supplier.xlsx
TemplateStoreRelative=0
PCB_PrintColor=2
SCH_PrintColor=0
PrintQuality=-3
SCH_ShowNoErc=-1
SCH_ShowParameter=-1
SCH_ShowProbes=-1
SCH_ShowBlankets=-1
SCH_NoERCSymbolsToShow="Thin Cross","Thick Cross","Small Cross",Checkbox,Triangle
SCH_ShowNote=-1
SCH_ShowNoteCollapsed=-1
SCH_ExpandLogicalToPhysical=-1
SCH_VariantName=
SCH_ExpandComponentDesignators=-1
SCH_ExpandNetlabels=0
SCH_ExpandPorts=0
SCH_ExpandSheetNumber=0
SCH_ExpandDocumentNumber=0
SCH_HasExpandLogicalToPhysicalSheets=0
SaveSettingsToOutJob=0
[Generic_EDE]
OutputDir=Project Outputs for Pcie_Brige_Test
[OutputGroup1]
Name=Netlist Outputs
Description=
@ -267,7 +402,7 @@ OutputDefault20=0
[OutputGroup2]
Name=Simulator Outputs
Description=
TargetPrinter=Print to PDF (Mac Desktop)
TargetPrinter=Parallels Shared Printer (副本 1)
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
[OutputGroup3]
@ -345,96 +480,168 @@ PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|Print
[OutputGroup4]
Name=Assembly Outputs
Description=
TargetPrinter=Print to PDF (Mac Desktop)
TargetPrinter=Parallels Shared Printer (副本 1)
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
OutputType1=Assembly
OutputName1=Assembly Drawings
OutputType1=Test Points For Assembly
OutputName1=Test Point Report
OutputDocumentPath1=
OutputVariantName1=[No Variations]
OutputDefault1=0
PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
OutputType2=Pick Place
OutputName2=Generates pick and place files
OutputDocumentPath2=
OutputVariantName2=[No Variations]
OutputDefault2=0
OutputType3=Test Points For Assembly
OutputName3=Test Point Report
Configuration2_Name1=ForceUpdateSettings
Configuration2_Item1=False
Configuration2_Name2=OutputConfigurationParameter1
Configuration2_Item2=Record=PickPlaceView|Units=Imperial|GenerateCSVFormat=True|GenerateTextFormat=False|ShowUnits=True|Separator=.|ExcludeFilterParam=False|IncludeVariations=False|IncludeStandardNoBOM=False|Filter= |FilterActive=False|YFlip=False|Column#1=Name:Designator,Fixed:True,Metric:False,Visible:True,Sort:None,Position:0|Column#2=Name:Comment,Fixed:True,Metric:False,Visible:True,Sort:None,Position:1|Column#3=Name:Layer,Fixed:True,Metric:False,Visible:True,Sort:None,Position:2|Column#4=Name:Footprint,Fixed:True,Metric:False,Visible:True,Sort:None,Position:3|Column#5=Name:Footprint Description,Fixed:True,Metric:False,Visible:False,Sort:None,Position:4|Column#6=Name:Center-X,Fixed:True,Metric:True,Visible:True,Sort:None,Position:5|Column#7=Name:Center-Y,Fixed:True,Metric:True,Visible:True,Sort:None,Position:6|Column#8=Name:Rotation,Fixed:True,Metric:False,Visible:True,Sort:None,Position:7|Column#9=Name:Description,Fixed:True,Metric:False,Visible:False,Sort:None,Position:8|Column#10=Name:ComponentKind,Fixed:True,Metric:False,Visible:False,Sort:None,Position:9|Column#11=Name:Height,Fixed:True,Metric:True,Visible:False,Sort:None,Position:10|Column#12=Name:Ref-X,Fixed:True,Metric:True,Visible:False,Sort:None,Position:11|Column#13=Name:Ref-Y,Fixed:True,Metric:True,Visible:False,Sort:None,Position:12|Column#14=Name:Pad-X,Fixed:True,Metric:True,Visible:False,Sort:None,Position:13|Column#15=Name:Pad-Y,Fixed:True,Metric:True,Visible:False,Sort:None,Position:14|Column#16=Name:Variation,Fixed:True,Metric:False,Visible:False,Sort:None,Position:15|Column#17=Name:Supplier,Fixed:False,Metric:False,Visible:False,Sort:None,Position:22|Column#18=Name:SuppliersPartNumber,Fixed:False,Metric:False,Visible:False,Sort:None,Position:23|Column#19=Name:LatestRevisionDate,Fixed:False,Metric:False,Visible:False,Sort:None,Position:18|Column#20=Name:Publisher,Fixed:False,Metric:False,Visible:False,Sort:None,Position:21|Column#21=Name:ComponentLink1Description,Fixed:False,Metric:False,Visible:False,Sort:None,Position:16|Column#22=Name:ComponentLink1URL,Fixed:False,Metric:False,Visible:False,Sort:None,Position:17|Column#23=Name:LatestRevisionNote,Fixed:False,Metric:False,Visible:False,Sort:None,Position:19|Column#24=Name:Package,Fixed:False,Metric:False,Visible:False,Sort:None,Position:20|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
OutputType3=Assembly
OutputName3=Assembly Drawings
OutputDocumentPath3=
OutputVariantName3=[No Variations]
OutputDefault3=0
PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=3.69|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=0|PaperKind=A4|PaperIndex=9
Configuration3_Name1=ForceUpdateSettings
Configuration3_Item1=False
Configuration3_Name2=OutputConfigurationParameter1
Configuration3_Item2=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration3_Name3=OutputConfigurationParameter2
Configuration3_Item3=IncludeBoardCutouts=False|IncludeBottomLayerComponents=False|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Top LayerAssembly Drawing|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration3_Name4=OutputConfigurationParameter3
Configuration3_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Hidden|FFill=Hidden|FPad=Hidden|FRegion=Hidden|FText=Hidden|FTrack=Hidden|FVia=Hidden|Layer=TopLayer|Polygon=Hidden|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration3_Name5=OutputConfigurationParameter4
Configuration3_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration3_Name6=OutputConfigurationParameter5
Configuration3_Item6=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Hidden|Layer=MultiLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration3_Name7=OutputConfigurationParameter6
Configuration3_Item7=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration3_Name8=OutputConfigurationParameter7
Configuration3_Item8=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical5|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration3_Name9=OutputConfigurationParameter8
Configuration3_Item9=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical13|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration3_Name10=OutputConfigurationParameter9
Configuration3_Item10=IncludeBoardCutouts=False|IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=False|IncludeViewports=True|Index=1|Mirror=False|Name=Bottom LayerAssembly Drawing|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration3_Name11=OutputConfigurationParameter10
Configuration3_Item11=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Hidden|FFill=Hidden|FPad=Hidden|FRegion=Hidden|FText=Hidden|FTrack=Hidden|FVia=Hidden|Layer=BottomLayer|Polygon=Hidden|PrintOutIndex=1|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration3_Name12=OutputConfigurationParameter11
Configuration3_Item12=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomOverlay|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration3_Name13=OutputConfigurationParameter12
Configuration3_Item13=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Hidden|Layer=MultiLayer|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration3_Name14=OutputConfigurationParameter13
Configuration3_Item14=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration3_Name15=OutputConfigurationParameter14
Configuration3_Item15=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical5|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration3_Name16=OutputConfigurationParameter15
Configuration3_Item16=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical13|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
[OutputGroup5]
Name=Fabrication Outputs
Description=
TargetPrinter=Print to PDF (Mac Desktop)
TargetPrinter=Parallels Shared Printer (副本 1)
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1
OutputType1=Board Stack Report
OutputName1=Report Board Stack
OutputType1=NC Drill
OutputName1=NC Drill Files
OutputDocumentPath1=
OutputVariantName1=
OutputDefault1=0
PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
OutputType2=CompositeDrill
OutputName2=Composite Drill Drawing
Configuration1_Name1=ForceUpdateSettings
Configuration1_Item1=False
Configuration1_Name2=OutputConfigurationParameter1
Configuration1_Item2=BoardEdgeRoutToolDia=2000000|GenerateBoardEdgeRout=False|GenerateDrilledSlotsG85=False|GenerateEIADrillFile=False|GenerateSeparatePlatedNonPlatedFiles=False|GenerateSeparateViaTypeFiles=False|NumberOfDecimals=4|NumberOfUnits=2|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Record=DrillView|Units=Imperial|ZeroesMode=SuppressTrailingZeroes|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
OutputType2=Mask
OutputName2=Solder/Paste Mask Prints
OutputDocumentPath2=
OutputVariantName2=
OutputDefault2=0
PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
OutputType3=Drill
OutputName3=Drill Drawing/Guides
OutputType3=IPC2581
OutputName3=IPC-2581 Files
OutputDocumentPath3=
OutputVariantName3=
OutputDefault3=0
PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
OutputType4=Final
OutputName4=Final Artwork Prints
OutputType4=Test Points
OutputName4=Test Point Report
OutputDocumentPath4=
OutputVariantName4=[No Variations]
OutputVariantName4=
OutputDefault4=0
PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
OutputType5=Gerber
OutputName5=Gerber Files
Configuration4_Name1=ForceUpdateSettings
Configuration4_Item1=False
Configuration4_Name2=OutputConfigurationParameter1
Configuration4_Item2=AdjacencyDistance=250000|GenerateCSVFormat=False|GenerateIPCFormat=True|GenerateSpreadSheetFormat=False|GenerateTextFormat=True|MergeNetTieNets=False|OriginPosition=Relative|OutlineLayer=56|OutputAdjancencies=False|OutputBoardOutline=False|OutputTraces=False|Record=TestPointView|ReportBottomLayerTestpoints=True|ReportTopLayerTestpoints=True|Units=Imperial|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
OutputType5=Plane
OutputName5=Power-Plane Prints
OutputDocumentPath5=
OutputVariantName5=[No Variations]
OutputVariantName5=
OutputDefault5=0
OutputType6=Gerber X2
OutputName6=Gerber X2 Files
PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
OutputType6=ODB
OutputName6=ODB++ Files
OutputDocumentPath6=
OutputVariantName6=
OutputVariantName6=[No Variations]
OutputDefault6=0
OutputType7=IPC2581
OutputName7=IPC-2581 Files
OutputType7=Drill
OutputName7=Drill Drawing/Guides
OutputDocumentPath7=
OutputVariantName7=
OutputDefault7=0
OutputType8=Mask
OutputName8=Solder/Paste Mask Prints
PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=3.69|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
Configuration7_Name1=ForceUpdateSettings
Configuration7_Item1=False
Configuration7_Name2=OutputConfigurationParameter1
Configuration7_Item2=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration7_Name3=OutputConfigurationParameter2
Configuration7_Item3=IncludeBoardCutouts=False|IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Drill Drawing For (Top Layer - Bottom Layer)|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration7_Name4=OutputConfigurationParameter3
Configuration7_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=DrillDrawing|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration7_Name5=OutputConfigurationParameter4
Configuration7_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration7_Name6=OutputConfigurationParameter5
Configuration7_Item6=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical5|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration7_Name7=OutputConfigurationParameter6
Configuration7_Item7=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical13|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration7_Name8=OutputConfigurationParameter7
Configuration7_Item8=IncludeBoardCutouts=False|IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=1|Mirror=False|Name=Drill Guide For (Top Layer - Bottom Layer)|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration7_Name9=OutputConfigurationParameter8
Configuration7_Item9=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=DrillGuide|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration7_Name10=OutputConfigurationParameter9
Configuration7_Item10=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration7_Name11=OutputConfigurationParameter10
Configuration7_Item11=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical5|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration7_Name12=OutputConfigurationParameter11
Configuration7_Item12=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical13|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
OutputType8=CompositeDrill
OutputName8=Composite Drill Drawing
OutputDocumentPath8=
OutputVariantName8=
OutputDefault8=0
PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
OutputType9=NC Drill
OutputName9=NC Drill Files
OutputType9=Board Stack Report
OutputName9=Report Board Stack
OutputDocumentPath9=
OutputVariantName9=
OutputDefault9=0
OutputType10=ODB
OutputName10=ODB++ Files
PageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
OutputType10=Gerber X2
OutputName10=Gerber X2 Files
OutputDocumentPath10=
OutputVariantName10=[No Variations]
OutputVariantName10=
OutputDefault10=0
OutputType11=Plane
OutputName11=Power-Plane Prints
OutputType11=Final
OutputName11=Final Artwork Prints
OutputDocumentPath11=
OutputVariantName11=
OutputVariantName11=[No Variations]
OutputDefault11=0
PageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
OutputType12=Test Points
OutputName12=Test Point Report
OutputType12=Gerber
OutputName12=Gerber Files
OutputDocumentPath12=
OutputVariantName12=
OutputVariantName12=[No Variations]
OutputDefault12=0
Configuration12_Name1=ForceUpdateSettings
Configuration12_Item1=False
Configuration12_Name2=OutputConfigurationParameter1
Configuration12_Item2=AddToAllLayerClasses.Set= |AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray,16908289~1|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=200000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=200000000|FilmYSize=160000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GenerateReports=True|GerberUnit=Imperial|GerberUnit=Imperial|IncludeUnconnectedMidLayerPads=False|LayerClassesMirror.Set= |LayerClassesPlot.Set= |LeadingAndTrailingZeroesMode=SuppressLeadingZeroes|MaxApertureSize=2500000|MinusApertureTolerance=50|MinusApertureTolerance=50|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NoRegularPolygons=False|NumberOfDecimals=4|NumberOfDecimals=4|OptimizeChangeLocationCommands=True|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray,16973830~1,16973832~1,16973834~1,16777217~1,16842753~1,16842754~1,16842751~1,16973835~1,16973833~1,16973831~1,16908289~1|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=True|PlotUsedDrillGuideLayerPairs=True|PlusApertureTolerance=50|PlusApertureTolerance=50|Record=GerberView|SoftwareArcs=False|Sorted=False|Sorted=False|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
[OutputGroup6]
Name=Report Outputs
@ -447,6 +654,20 @@ OutputDocumentPath1=
OutputVariantName1=[No Variations]
OutputDefault1=0
PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
Configuration1_Name1=ColumnNameFormat
Configuration1_Item1=CaptionAsName
Configuration1_Name2=ForceUpdateSettings
Configuration1_Item2=False
Configuration1_Name3=General
Configuration1_Item3=OpenExported=False|AddToProject=False|ReportBOMViolationsInMessages=False|ForceFit=False|NotFitted=False|Database=False|DatabasePriority=False|IncludePcbData=False|IncludeVaultData=False|IncludeCloudData=False|IncludeDocumentData=True|IncludeAlternatives=False|ShowExportOptions=True|TemplateFilename=C:\Users\Public\Documents\Altium\AD22\Templates\BOM Template Single Supplier.xlsx|TemplateVaultGuid=|TemplateItemGuid=|TemplateRevisionGuid=|BatchMode=5|FormWidth=1200|FormHeight=710|SupplierProdQty=1|SupplierAutoQty=False|SupplierUseCachedPricing=False|SupplierCurrency=USD|SolutionsPerItem=1|SuppliersPerSolution=1|ViewType=1|UseDirectApi=False|BomSetName=
Configuration1_Name4=GroupOrder
Configuration1_Item4=Comment=True|Footprint=True
Configuration1_Name5=SortOrder
Configuration1_Item5=Designator=Up|Comment=Up|Footprint=Up
Configuration1_Name6=VisibleOrder
Configuration1_Item6=Comment=120|Designator=120|Footprint=120|Quantity=120
Configuration1_Name7=VisibleOrder_Flat
Configuration1_Item7=Comment=120|Designator=120|Footprint=120|Quantity=120
OutputType2=BOM_ReportCompare
OutputName2=BOM Compare
OutputDocumentPath2=
@ -1116,4 +1337,22 @@ ComparisonOptions5=Kind=Structure Class|MinPercent=75|MinMatch=3|ShowMatch=0|Use
[SmartPDF]
PageOptions=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
Configuration_Name1=OutputConfigurationParameter1
Configuration_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration_Name2=OutputConfigurationParameter2
Configuration_Item2=IncludeBoardCutouts=False|IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Top LayerAssembly Drawing|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=True|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration_Name3=OutputConfigurationParameter3
Configuration_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration_Name4=OutputConfigurationParameter4
Configuration_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopSolder|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration_Name5=OutputConfigurationParameter5
Configuration_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration_Name6=OutputConfigurationParameter6
Configuration_Item6=IncludeBoardCutouts=False|IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=1|Mirror=True|Name=Bottom LayerAssembly Drawing|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=True|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration_Name7=OutputConfigurationParameter7
Configuration_Item7=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomOverlay|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration_Name8=OutputConfigurationParameter8
Configuration_Item8=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Configuration_Name9=OutputConfigurationParameter9
Configuration_Item9=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|DrillType=Regular|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomSolder|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer|DocumentPath=C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc

BIN
Pcie_Brige_pwr.SchDoc
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BIN
Pcie_PCB.PcbLib
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61
Project Logs for Pcie_Brige_Test/PCIE_Brige_PCB PCB ECO 2022-11-22 17-24-45.LOG Normal file
View File

@ -0,0 +1,61 @@
Change Component Comment : Designator=U1 Old Comment=P17C9X2G608GP New Comment=PI7C9X2G608GP
Change Component Kind : Designator=TPD1 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=TP2 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=TP1 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=TPD4 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=TPD3 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=TPD2 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P24 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P23 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P22 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P28 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P26 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P25 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=TPD5 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=TPU3 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=TPU2 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=TPU1 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=TPU6 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=TPU5 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=TPU4 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=TPD8 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=TPD7 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=TPD6 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=TPD11 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=TPD10 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=TPD9 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P5 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P4 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P3 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P8 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P7 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P6 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=H3 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=H2 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=H1 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P2 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P1 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=H4 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P9 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P18 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P17 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P16 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P21 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P20 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P19 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P12 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P11 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P10 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P15 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P14 Old Kind=Standard New Kind=Standard (No BOM)
Change Component Kind : Designator=P13 Old Kind=Standard New Kind=Standard (No BOM)
Added Pin To Net: NetName=PCIE_SW_VDDR_3V3 Pin=U1-D14
Change Net Color : Old Net Color=RGB(158, 161, 117) New Net Color=Default
Change Net Color : Old Net Color=RGB(158, 161, 117) New Net Color=Default
Change Net Color : Old Net Color=RGB(158, 161, 117) New Net Color=Default
Change Net Color : Old Net Color=RGB(158, 161, 117) New Net Color=Default
Change Net Color : Old Net Color=RGB(158, 161, 117) New Net Color=Default
Change Net Color : Old Net Color=RGB(158, 161, 117) New Net Color=Default
Added Room: Name=Pcie_Brige_Cfg
Added Room: Name=Pcie_Brige_Core
Added Room: Name=Pcie_Brige_pwr

36
Project Outputs for Pcie_Brige_Test/Design Rule Check - PCIE_Brige_PCB.drc
View File

@ -1,36 +0,0 @@
Protel Design System Design Rule Check
PCB File : C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Date : 2022/11/21
Time : 22:54:09
Processing Rule : Clearance Constraint (Gap=6mil) (All),(All)
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0
Processing Rule : Width Constraint (Min=4mil) (Max=10mil) (Preferred=6mil) (All)
Rule Violations :0
Processing Rule : Routing Layers(All)
Rule Violations :0
Processing Rule : Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=15.748mil) (PreferredHoleWidth=11.811mil) (MinWidth=11.811mil) (MaxWidth=23.622mil) (PreferedWidth=19.685mil) (All)
Rule Violations :0
Processing Rule : Differential Pairs Uncoupled Length using the Gap Constraints (Min=4mil) (Max=10mil) (Prefered=6mil) and Width Constraints (Min=6mil) (Max=15mil) (Prefered=6mil) (All)
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
Rule Violations :0
Violations Detected : 0
Waived Violations : 0
Time Elapsed : 00:00:01

308
Project Outputs for Pcie_Brige_Test/Design Rule Check - PCIE_Brige_PCB.html
View File

@ -1,308 +0,0 @@
<html>
<head>
<META http-equiv="Content-Type" content="text/html">
<style type="text/css">
h1, h2, h3, h4, h5, h6 {
font-family : segoe ui;
color : black;
background-color : #EDE7D9;
padding: 0.3em;
}
h1 {
font-size: 1.2em;
}
h2 {
font-size: 1.2em;
}
body {
font-family : segoe ui;
}
td, th {
padding: 0.5em;
text-align : left;
width: 10em;
}
th {
background-color : #EEEEEE;
}
th.column1, td.column1 {
text-align: left;
width : auto;
}
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</style><script type="text/javascript">
function coordToMils(coord) {
var number = coord / 10000;
if (number != number.toFixed(3))
number = number.toFixed(3);
return number + 'mil'
}
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</script><title>Design Rule Verification Report</title>
</head>
<body onload=""><img ALT="Altium" src="
file://C:\Users\Public\Documents\Altium\AD22\Templates\AD_logo.png
"><h1>Design Rule Verification Report</h1>
<table class="header_holder">
<td class="column1">
<table class="front_matter">
<tr class="front_matter">
<td class="front_matter_column1">Date:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3">2022/11/21</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Time:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3">22:54:09</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Elapsed Time:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3">00:00:01</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Filename:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3"><a href="file:///C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc" class="file"><acronym title="C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc">C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc</acronym></a></td>
</tr>
</table>
</td>
<td class="column2">
<table class="DRC_summary_header">
<tr>
<td class="DRC_summary_header_col1">Warnings:</td>
<td class="DRC_summary_header_col2"></td>
<td class="DRC_summary_header_col3">0</td></tr>
<tr>
<td class="DRC_summary_header_col1">Rule Violations:</td>
<td class="DRC_summary_header_col2"></td>
<td class="DRC_summary_header_col3">0</td></tr>
</table>
</td>
</table><a name="IDJYZLNTZZBM1NDROISYISOFLWRIQAHE5VKF2R33NK3RKWUTPZP3OF"><h2>Summary</h2></a><table>
<tr>
<th class="column1">Warnings</th>
<th class="column2">Count</th>
</tr>
<tr>
<td style="font-weight : bold; text-align : right" class="column1">Total</td>
<td style="font-weight : bold" class="column2">0</td>
</tr>
</table><br><table>
<tr>
<th class="column1">Rule Violations</th>
<th class="column2">Count</th>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDAD0CDRRMUR3ZCE5RQLWZWFVO0MDEZVS5YWXQWLIQU12V2K2SACID">Clearance Constraint (Gap=6mil) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDYQ0X0KORH4DEITHDZX5DMUDOTMNDP0M2QTVUECN4OET4L1GNR4VC">Short-Circuit Constraint (Allowed=No) (All),(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDHJPAZM04KGL1KGYEZL0C2OJSENJZRVX5COC4BDHVOLJI2YO0SBMI">Un-Routed Net Constraint ( (All) )</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDSF43P445WB2LIJ0DKZNQBN3QYLFCYDCOJXJWYIOFPFQ0ACIJSHFE">Modified Polygon (Allow modified: No), (Allow shelved: No)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDQRLAHWE2FS51HPTPGPWGRU0CFBKIY0S5U5ON5DPAONEVRVLSK0K">Width Constraint (Min=4mil) (Max=10mil) (Preferred=6mil) (All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#IDSOYQ2PZ2IDEX2WWS2OL2MLRXPMYS3NO0BQTV2BTYHZRBPS4533D">Routing Layers(All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDYJMLYP2D3FFPSVAWBXLQIRDTIZXVSFKGP2OSVBVHGVNP2VQ1ZRF">Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=15.748mil) (PreferredHoleWidth=11.811mil) (MinWidth=11.811mil) (MaxWidth=23.622mil) (PreferedWidth=19.685mil) (All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
<td class="column1"><a href="#ID0FK5YGCEASBFEBEOJDJMQYY0HO2QDXSNPRMZKNHUXQWJ0XKTN3AL">Differential Pairs Uncoupled Length using the Gap Constraints (Min=4mil) (Max=10mil) (Prefered=6mil) and Width Constraints (Min=6mil) (Max=15mil) (Prefered=6mil) (All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDJEFXHB03YN3UGOPHMU5VA3WOFBZKPM34BRJCNEKGOPEJFSHKJQAH">Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)</a></td>
<td class="column2">0</td>
</tr>
<tr>
<td style="font-weight : bold; text-align : right" class="column1">Total</td>
<td style="font-weight : bold" class="column2">0</td>
</tr>
</table><br></body>
</html>

0
Project Outputs for Pcie_Brige_Test/PCIE_Brige_PCB-macro.APR_LIB Normal file
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18
Project Outputs for Pcie_Brige_Test/PCIE_Brige_PCB.DRR Normal file
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@ -0,0 +1,18 @@
----------------------------------------------------------------------------------------------------------------------------------
NCDrill File Report For: PCIE_Brige_PCB.PcbDoc 2022/11/22 17:26:18
----------------------------------------------------------------------------------------------------------------------------------
Layer Pair : Top Layer to Bottom Layer
ASCII RoundHoles File : PCIE_Brige_PCB.TXT
Tool Hole Size Hole Tolerance Hole Type Hole Count Plated Tool Travel
----------------------------------------------------------------------------------------------------------------------------------
T1 12mil (0.3mm) Round 68 PTH 9.21inch (233.96mm)
T2 24mil (0.599mm) Round 40 PTH 4.87inch (123.73mm)
T3 32mil (0.8mm) Round 32 PTH 7.95inch (201.90mm)
T4 35mil (0.899mm) Round 32 PTH 6.87inch (174.48mm)
T5 138mil (3.5mm) Round 4 PTH 5.91inch (150.09mm)
----------------------------------------------------------------------------------------------------------------------------------
Totals 176
Total Processing Time (hh:mm:ss) : 00:00:00

22
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@ -0,0 +1,22 @@
------------------------------------------------------------------------------------------
Gerber File Extension Report For: PCIE_Brige_PCB.GBR 2022/11/22 17:25:24
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
Layer Extension Layer Description
------------------------------------------------------------------------------------------
.GTO Top Overlay
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.GP2 VCC03
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------------------------------------------------------------------------------------------

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1560
Project Outputs for Pcie_Brige_Test/PCIE_Brige_PCB.GD1 Normal file
View File

File diff suppressed because it is too large Load Diff

890
Project Outputs for Pcie_Brige_Test/PCIE_Brige_PCB.GG1 Normal file
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@ -0,0 +1,890 @@
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M02*

344
Project Outputs for Pcie_Brige_Test/PCIE_Brige_PCB.GM1 Normal file
View File

@ -0,0 +1,344 @@
G04*
G04 #@! TF.GenerationSoftware,Altium Limited,Altium Designer,22.0.2 (36)*
G04*
G04 Layer_Color=16711935*
%FSLAX24Y24*%
%MOIN*%
G70*
G04*
G04 #@! TF.SameCoordinates,CD407462-B920-417C-8B87-A3646CBED1B3*
G04*
G04*
G04 #@! TF.FilePolarity,Positive*
G04*
G01*
G75*
%ADD11C,0.0100*%
%ADD14C,0.0197*%
%ADD15C,0.0098*%
%ADD16C,0.0060*%
D11*
X25591Y-1850D02*
Y0D01*
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X-2100Y600D02*
X-1900Y0D01*
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X-1700Y19085D01*
X-2100D02*
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Y0D02*
Y7573D01*
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X-1700Y19085D01*
X-2100D02*
X-1900Y19685D01*
Y0D02*
Y7573D01*
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X-2000Y0D02*
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D14*
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D15*
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D16*
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Y-1610D01*
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Y-1610D01*
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Y-1710D01*
X13685D01*
X13785Y-1810D01*
Y-2110D01*
Y-1810D01*
X13885Y-1710D01*
X13985Y-1810D01*
Y-2110D01*
X14185D02*
Y-1710D01*
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X-2140Y8133D02*
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X-1640Y7733D01*
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X-2040Y10432D01*
X-1640D01*
X-1540Y10332D01*
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X-1640Y10032D01*
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X-1540Y10632D02*
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M02*

432
Project Outputs for Pcie_Brige_Test/PCIE_Brige_PCB.GP1 Normal file
View File

@ -0,0 +1,432 @@
G04*
G04 #@! TF.GenerationSoftware,Altium Limited,Altium Designer,22.0.2 (36)*
G04*
G04 Layer_Physical_Order=2*
G04 Layer_Color=1930808*
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G70*
G04*
G04 #@! TF.SameCoordinates,CD407462-B920-417C-8B87-A3646CBED1B3*
G04*
G04*
G04 #@! TF.FilePolarity,Negative*
G04*
G01*
G75*
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D11*
X25591Y-1850D02*
Y0D01*
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Y0D01*
X-2100Y600D02*
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Y0D02*
Y7573D01*
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X-2000Y0D02*
X0D01*
X-2000Y19685D02*
X0D01*
D14*
Y0D02*
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Y0D02*
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Y0D02*
Y19685D01*
D15*
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X0D02*
X600Y-1550D01*
X0Y-1750D02*
X600Y-1950D01*
X14745Y-1750D02*
X25591D01*
X0D02*
X10526D01*
D16*
X11086Y-1510D02*
X10886Y-1610D01*
X10686Y-1810D01*
Y-2010D01*
X10786Y-2110D01*
X10986D01*
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Y-1910D01*
X10986Y-1810D01*
X10686D01*
X11686Y-1510D02*
X11286D01*
Y-1810D01*
X11486Y-1710D01*
X11586D01*
X11686Y-1810D01*
Y-2010D01*
X11586Y-2110D01*
X11386D01*
X11286Y-2010D01*
X11886Y-2110D02*
Y-2010D01*
X11985D01*
Y-2110D01*
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X12385Y-1610D02*
X12485Y-1510D01*
X12685D01*
X12785Y-1610D01*
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X12385Y-2010D01*
Y-1610D01*
X12985D02*
X13085Y-1510D01*
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X13385Y-1610D01*
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X12985Y-2010D01*
Y-1610D01*
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Y-1710D01*
X13685D01*
X13785Y-1810D01*
Y-2110D01*
Y-1810D01*
X13885Y-1710D01*
X13985Y-1810D01*
Y-2110D01*
X14185D02*
Y-1710D01*
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X14385Y-1810D01*
Y-2110D01*
Y-1810D01*
X14485Y-1710D01*
X14585Y-1810D01*
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546
Project Outputs for Pcie_Brige_Test/PCIE_Brige_PCB.GP2 Normal file
View File

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5351
Project Outputs for Pcie_Brige_Test/PCIE_Brige_PCB.GTL Normal file
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File diff suppressed because it is too large Load Diff

22760
Project Outputs for Pcie_Brige_Test/PCIE_Brige_PCB.GTO Normal file
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File diff suppressed because it is too large Load Diff

628
Project Outputs for Pcie_Brige_Test/PCIE_Brige_PCB.GTP Normal file
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@ -0,0 +1,628 @@
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856
Project Outputs for Pcie_Brige_Test/PCIE_Brige_PCB.GTS Normal file
View File

@ -0,0 +1,856 @@
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D03*
X13051Y6693D02*
D03*
X12717D02*
D03*
D22*
X4350Y6516D02*
D03*
X4370Y7539D02*
D03*
X17539Y11437D02*
D03*
X20039Y5197D02*
D03*
Y6102D02*
D03*
X21122Y10157D02*
D03*
X20000Y10138D02*
D03*
X18780Y10177D02*
D03*
Y11417D02*
D03*
X20000Y11476D02*
D03*
Y12402D02*
D03*
X17539D02*
D03*
X8996Y17894D02*
D03*
X4843D02*
D03*
X17539Y10138D02*
D03*
X8012Y17894D02*
D03*
X18780Y12382D02*
D03*
X5925Y17894D02*
D03*
X6949D02*
D03*
X23800Y13100D02*
D03*
Y12100D02*
D03*
Y11100D02*
D03*
Y10100D02*
D03*
Y9100D02*
D03*
Y8100D02*
D03*
Y7100D02*
D03*
X9772Y1339D02*
D03*
X10772D02*
D03*
X11772D02*
D03*
X12772D02*
D03*
X13772D02*
D03*
X7618Y4173D02*
D03*
X6618D02*
D03*
X18996Y4114D02*
D03*
X17996D02*
D03*
X2050Y12350D02*
D03*
Y13350D02*
D03*
Y14350D02*
D03*
X2008Y8079D02*
D03*
Y9079D02*
D03*
X16950Y16650D02*
D03*
X17950D02*
D03*
X18950D02*
D03*
X19950D02*
D03*
D23*
X7008Y8650D02*
D03*
Y10020D02*
D03*
Y6100D02*
D03*
Y7400D02*
D03*
Y10780D02*
D03*
Y12000D02*
D03*
Y13260D02*
D03*
Y14488D02*
D03*
X4469Y10228D02*
D03*
D24*
X7008Y8150D02*
D03*
X13750Y4028D02*
D03*
X10059D02*
D03*
X11319D02*
D03*
X12550D02*
D03*
X15000D02*
D03*
X16200D02*
D03*
X23631Y2953D02*
D03*
X22936Y2664D02*
D03*
X22647Y1969D02*
D03*
X22936Y1273D02*
D03*
X23631Y984D02*
D03*
X24327Y1273D02*
D03*
Y2664D02*
D03*
X24616Y1969D02*
D03*
X2953D02*
D03*
X2664Y2664D02*
D03*
Y1273D02*
D03*
X1969Y984D02*
D03*
X1273Y1273D02*
D03*
X984Y1969D02*
D03*
X1273Y2664D02*
D03*
X1969Y2953D02*
D03*
X2953Y17731D02*
D03*
X2664Y18427D02*
D03*
Y17036D02*
D03*
X1969Y16747D02*
D03*
X1273Y17036D02*
D03*
X984Y17731D02*
D03*
X1273Y18427D02*
D03*
X1969Y18716D02*
D03*
X23631D02*
D03*
X22936Y18427D02*
D03*
X22647Y17731D02*
D03*
X22936Y17036D02*
D03*
X23631Y16747D02*
D03*
X24327Y17036D02*
D03*
Y18427D02*
D03*
X24616Y17731D02*
D03*
X7008Y9520D02*
D03*
Y5600D02*
D03*
Y6900D02*
D03*
Y11280D02*
D03*
Y12500D02*
D03*
Y13760D02*
D03*
Y14988D02*
D03*
X4469Y10728D02*
D03*
X13050Y16500D02*
D03*
X15550D02*
D03*
X14300D02*
D03*
X12300D02*
D03*
X11050D02*
D03*
D25*
X23800Y6100D02*
D03*
X2050Y11350D02*
D03*
X2008Y10079D02*
D03*
D26*
X14772Y1339D02*
D03*
X8618Y4173D02*
D03*
X19996Y4114D02*
D03*
X20950Y16650D02*
D03*
D27*
X13250Y4028D02*
D03*
X9559D02*
D03*
X10819D02*
D03*
X12050D02*
D03*
X14500D02*
D03*
X15700D02*
D03*
X13550Y16500D02*
D03*
X16050D02*
D03*
X14800D02*
D03*
X11800D02*
D03*
X10550D02*
D03*
D28*
X23631Y1969D02*
D03*
X1969D02*
D03*
Y17731D02*
D03*
X23631D02*
D03*
M02*

2
Project Outputs for Pcie_Brige_Test/PCIE_Brige_PCB.LDP Normal file
View File

@ -0,0 +1,2 @@
Layer Pairs Export File for PCB: C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
LayersSetName=Top_Bot_Thru_Holes|DrillFile=pcie_brige_pcb.txt|DrillLayers=gtl,gp1,gp2,gbl

294
Project Outputs for Pcie_Brige_Test/PCIE_Brige_PCB.REP Normal file
View File

@ -0,0 +1,294 @@
*************************************************************
FileName = PCIE_Brige_PCB.GBR
AutoAperture = True
*************************************************************
Generating : Top Layer
File : PCIE_Brige_PCB.GTL
Adding Layer : Top Layer
Adding Layer : Mechanical 1
Adding Layer : Multi-Layer
Used DCodes :
D11
D14
D15
D16
D17
D18
D19
D29
D30
D31
D32
D33
D34
D35
D36
*************************************************************
*************************************************************
Generating : GND02
File : PCIE_Brige_PCB.GP1
Adding Layer : GND02
Adding Layer : Mechanical 1
Adding Layer : Multi-Layer
Used DCodes :
D11
D14
D15
D16
D37
D38
D39
D40
*************************************************************
*************************************************************
Generating : VCC03
File : PCIE_Brige_PCB.GP2
Adding Layer : VCC03
Adding Layer : Mechanical 1
Adding Layer : Multi-Layer
Used DCodes :
D11
D14
D15
D16
D37
D38
D39
D40
D41
D42
*************************************************************
*************************************************************
Generating : Bottom Layer
File : PCIE_Brige_PCB.GBL
Adding Layer : Bottom Layer
Adding Layer : Mechanical 1
Adding Layer : Multi-Layer
Used DCodes :
D11
D14
D15
D16
D19
D29
D30
D31
D32
D33
D34
D35
D36
*************************************************************
*************************************************************
Generating : Bottom Paste
File : PCIE_Brige_PCB.GBP
Adding Layer : Bottom Paste
Adding Layer : Mechanical 1
Adding Layer : Bottom Layer
Adding Layer : Multi-Layer
Used DCodes :
D11
D14
D15
D16
*************************************************************
*************************************************************
Generating : Mechanical 1
File : PCIE_Brige_PCB.GM1
Adding Layer : Mechanical 1
Adding Layer : Mechanical 1
Used DCodes :
D11
D14
D15
D16
*************************************************************
*************************************************************
Generating : Bottom Overlay
File : PCIE_Brige_PCB.GBO
Adding Layer : Bottom Overlay
Adding Layer : Mechanical 1
Used DCodes :
D11
D14
D15
D16
*************************************************************
*************************************************************
Generating : Top Overlay
File : PCIE_Brige_PCB.GTO
Adding Layer : Top Overlay
Adding Layer : Mechanical 1
Used DCodes :
D10
D11
D12
D13
D14
D15
D16
*************************************************************
*************************************************************
Generating : Top Paste
File : PCIE_Brige_PCB.GTP
Adding Layer : Top Paste
Adding Layer : Mechanical 1
Adding Layer : Top Layer
Adding Layer : Multi-Layer
Used DCodes :
D11
D14
D15
D16
D17
D18
D19
*************************************************************
*************************************************************
Generating : Top Solder
File : PCIE_Brige_PCB.GTS
Adding Layer : Top Solder
Adding Layer : Mechanical 1
Adding Layer : Top Layer
Adding Layer : Multi-Layer
Used DCodes :
D11
D14
D15
D16
D20
D21
D22
D23
D24
D25
D26
D27
D28
*************************************************************
*************************************************************
Generating : Bottom Solder
File : PCIE_Brige_PCB.GBS
Adding Layer : Bottom Solder
Adding Layer : Mechanical 1
Adding Layer : Bottom Layer
Adding Layer : Multi-Layer
Used DCodes :
D11
D14
D15
D16
D22
D23
D24
D25
D26
D27
D28
*************************************************************
*************************************************************
Generating : Drill Drawing
File : PCIE_Brige_PCB.GD1
Adding Layer : Mechanical 1
Adding Drill Pair : Top Layer-Bottom Layer
Adding Layer : Drill Drawing
Used DCodes :
D11
D14
D15
D16
D43
D44
*************************************************************
*************************************************************
Generating : Drill Guide
File : PCIE_Brige_PCB.GG1
Adding Layer : Mechanical 1
Adding Drill Pair : Top Layer-Bottom Layer
Adding Layer : Drill Guide
Used DCodes :
D11
D14
D15
D16
D43
*************************************************************

5
Project Outputs for Pcie_Brige_Test/PCIE_Brige_PCB.RUL Normal file
View File

@ -0,0 +1,5 @@
DRC Rules Export File for PCB: C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=4.00
RuleKind=Width|RuleName=Width|Scope=Board|Minimum=4.00
RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=6.00
RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0

193
Project Outputs for Pcie_Brige_Test/PCIE_Brige_PCB.TXT Normal file
View File

@ -0,0 +1,193 @@
M48
;Layer_Color=9474304
;FILE_FORMAT=2:4
INCH,LZ
;TYPE=PLATED
T1F00S00C0.0118
T2F00S00C0.0236
T3F00S00C0.0315
T4F00S00C0.0354
T5F00S00C0.1378
%
T01
X021142Y009508
X023071Y008091
X02315Y012067
X01939Y011437
X016929Y011417
X015394Y011811
X015
X014622Y011859
X014218Y011758
X014667Y011378
Y010984
Y01061
X014825Y010406
X014626Y010197
X013839
Y010551
X013425
Y010197
Y009823
Y009429
X013839
Y009823
Y010984
X013425
X012657
X012264
Y010571
Y010197
Y009823
X012657
Y010197
Y010571
Y009409
X012264
X011473Y009397
X011437Y009055
X011083Y008661
X010689Y008268
X010394Y007343
X009803Y007756
X010591Y006358
X012069Y008438
X013644
X014272Y008672
X014626Y008268
X015Y009055
Y009429
X013051Y009075
X011102Y009823
X011476Y010217
X011496Y010591
X011281Y0108
X011083Y011004
Y011398
X011102Y011772
X010494Y011981
X012069
X012264Y011791
X012997Y011729
X013445Y012185
X016949Y003484
X017205Y003031
X005157Y006496
Y007539
X010276Y013386
X016929Y015935
X017953
X020965Y015925
T02
X007008Y0056
Y0061
Y0069
Y0074
Y00815
Y00865
Y00952
Y01002
Y01078
Y01128
Y012
Y0125
X004469Y010728
Y010228
X009559Y004028
X010059
X010819
X011319
X01205
X01255
X01325
X01375
X0145
X015
X0157
X0162
X01605Y0165
X01555
X0148
X0143
X01355
X01305
X0123
X0118
X01105
X01055
X007008Y014988
Y014488
Y01376
Y01326
T03
X022936Y001273
X022647Y001969
X022936Y002664
X023631Y002953
X024327Y002664
X024616Y001969
X024327Y001273
X023631Y000984
X002664Y001273
X002953Y001969
X002664Y002664
X001969Y002953
X001273Y002664
X000984Y001969
X001273Y001273
X001969Y000984
Y016747
X002664Y017036
X002953Y017731
X002664Y018427
X001969Y018716
X001273Y018427
X000984Y017731
X001273Y017036
X022936
X022647Y017731
X022936Y018427
X023631Y018716
X024327Y018427
X024616Y017731
X024327Y017036
X023631Y016747
T04
X018996Y004114
X019996
X0238Y0061
Y0071
Y0081
Y0091
Y0101
Y0111
Y0121
Y0131
X017996Y004114
X014772Y001339
X013772
X012772
X011772
X010772
X009772
X008618Y004173
X007618
X006618
X002008Y008079
Y009079
Y010079
X00205Y01135
Y01235
Y01335
Y01435
X01695Y01665
X01795
X01895
X01995
X02095
T05
X023631Y001969
X001969
Y017731
X023631
M30

35
Project Outputs for Pcie_Brige_Test/PCIE_Brige_PCB.apr Normal file
View File

@ -0,0 +1,35 @@
D10 ROUNDED 15.748 15.748 0.000 LINE 0.000
D11 ROUNDED 10.000 10.000 0.000 LINE 0.000
D12 ROUNDED 3.937 3.937 0.000 LINE 0.000
D13 ROUNDED 7.874 7.874 0.000 LINE 0.000
D14 ROUNDED 19.685 19.685 0.000 LINE 0.000
D15 ROUNDED 9.842 9.842 0.000 LINE 0.000
D16 ROUNDED 6.000 6.000 0.000 LINE 0.000
D17 ROUNDED 13.780 13.780 0.000 FLASH 0.000
D18 RECTANGULAR 23.622 25.591 0.000 FLASH 0.000
D19 ROUNDED 59.055 59.055 0.000 FLASH 0.000
D20 ROUNDED 21.779 21.779 0.000 FLASH 0.000
D21 RECTANGULAR 27.622 29.591 0.000 FLASH 0.000
D22 ROUNDED 67.055 67.055 0.000 FLASH 0.000
D23 RECTANGULAR 47.370 47.370 0.000 FLASH 270.000
D24 ROUNDED 47.370 47.370 0.000 FLASH 0.000
D25 RECTANGULAR 67.055 67.055 0.000 FLASH 90.000
D26 RECTANGULAR 67.055 67.055 0.000 FLASH 180.000
D27 RECTANGULAR 47.370 47.370 0.000 FLASH 0.000
D28 ROUNDED 283.591 283.591 0.000 FLASH 0.000
D29 RECTANGULAR 39.370 39.370 0.000 FLASH 270.000
D30 ROUNDED 39.370 39.370 0.000 FLASH 0.000
D31 RECTANGULAR 59.055 59.055 0.000 FLASH 90.000
D32 RECTANGULAR 59.055 59.055 0.000 FLASH 180.000
D33 RECTANGULAR 39.370 39.370 0.000 FLASH 0.000
D34 ROUNDED 275.591 275.591 0.000 FLASH 0.000
D35 ROUNDED 17.716 17.716 0.000 FLASH 0.000
D36 ROUNDED 19.685 19.685 0.000 FLASH 0.000
D37 ROUNDED 40.000 40.000 0.000 LINE 0.000
D38 ROUNDED 39.622 39.622 0.000 FLASH 0.000
D39 ROUNDED 51.433 51.433 0.000 FLASH 0.000
D40 ROUNDED 27.811 27.811 0.000 FLASH 0.000
D41 ROUNDED 153.795 153.795 0.000 FLASH 0.000
D42 ROUNDED 47.496 47.496 0.000 FLASH 0.000
D43 ROUNDED 2.000 2.000 0.000 LINE 0.000
D44 ROUNDED 2.667 2.667 0.000 LINE 0.000

628
Project Outputs for Pcie_Brige_Test/PcieBrige-ASM/PCIE_Brige_PCB.GTP Normal file
View File

@ -0,0 +1,628 @@
G04*
G04 #@! TF.GenerationSoftware,Altium Limited,Altium Designer,22.0.2 (36)*
G04*
G04 Layer_Color=8421504*
%FSLAX24Y24*%
%MOIN*%
G70*
G04*
G04 #@! TF.SameCoordinates,CD407462-B920-417C-8B87-A3646CBED1B3*
G04*
G04*
G04 #@! TF.FilePolarity,Positive*
G04*
G01*
G75*
%ADD11C,0.0100*%
%ADD14C,0.0197*%
%ADD15C,0.0098*%
%ADD16C,0.0060*%
%ADD17C,0.0138*%
%ADD18R,0.0236X0.0256*%
%ADD19C,0.0591*%
D11*
X25591Y-1850D02*
Y0D01*
X0Y-1850D02*
Y0D01*
X-2100Y600D02*
X-1900Y0D01*
X-1700Y600D01*
X-1900Y19685D02*
X-1700Y19085D01*
X-2100D02*
X-1900Y19685D01*
Y0D02*
Y7573D01*
Y11792D02*
Y19685D01*
X-2000Y0D02*
X0D01*
X-2000Y19685D02*
X0D01*
D14*
Y0D02*
Y19685D01*
Y0D02*
X25591D01*
X0Y19685D02*
X25591D01*
Y0D02*
Y19685D01*
D15*
X24991Y-1950D02*
X25591Y-1750D01*
X24991Y-1550D02*
X25591Y-1750D01*
X0D02*
X600Y-1550D01*
X0Y-1750D02*
X600Y-1950D01*
X14745Y-1750D02*
X25591D01*
X0D02*
X10526D01*
D16*
X11086Y-1510D02*
X10886Y-1610D01*
X10686Y-1810D01*
Y-2010D01*
X10786Y-2110D01*
X10986D01*
X11086Y-2010D01*
Y-1910D01*
X10986Y-1810D01*
X10686D01*
X11686Y-1510D02*
X11286D01*
Y-1810D01*
X11486Y-1710D01*
X11586D01*
X11686Y-1810D01*
Y-2010D01*
X11586Y-2110D01*
X11386D01*
X11286Y-2010D01*
X11886Y-2110D02*
Y-2010D01*
X11985D01*
Y-2110D01*
X11886D01*
X12385Y-1610D02*
X12485Y-1510D01*
X12685D01*
X12785Y-1610D01*
Y-2010D01*
X12685Y-2110D01*
X12485D01*
X12385Y-2010D01*
Y-1610D01*
X12985D02*
X13085Y-1510D01*
X13285D01*
X13385Y-1610D01*
Y-2010D01*
X13285Y-2110D01*
X13085D01*
X12985Y-2010D01*
Y-1610D01*
X13585Y-2110D02*
Y-1710D01*
X13685D01*
X13785Y-1810D01*
Y-2110D01*
Y-1810D01*
X13885Y-1710D01*
X13985Y-1810D01*
Y-2110D01*
X14185D02*
Y-1710D01*
X14285D01*
X14385Y-1810D01*
Y-2110D01*
Y-1810D01*
X14485Y-1710D01*
X14585Y-1810D01*
Y-2110D01*
X-2140Y8133D02*
Y7733D01*
X-1840D01*
X-1940Y7933D01*
Y8033D01*
X-1840Y8133D01*
X-1640D01*
X-1540Y8033D01*
Y7833D01*
X-1640Y7733D01*
X-2040Y8333D02*
X-2140Y8433D01*
Y8633D01*
X-2040Y8733D01*
X-1640D01*
X-1540Y8633D01*
Y8433D01*
X-1640Y8333D01*
X-2040D01*
X-1540Y8933D02*
X-1640D01*
Y9033D01*
X-1540D01*
Y8933D01*
X-2040Y9433D02*
X-2140Y9533D01*
Y9732D01*
X-2040Y9832D01*
X-1640D01*
X-1540Y9732D01*
Y9533D01*
X-1640Y9433D01*
X-2040D01*
Y10032D02*
X-2140Y10132D01*
Y10332D01*
X-2040Y10432D01*
X-1640D01*
X-1540Y10332D01*
Y10132D01*
X-1640Y10032D01*
X-2040D01*
X-1540Y10632D02*
X-1940D01*
Y10732D01*
X-1840Y10832D01*
X-1540D01*
X-1840D01*
X-1940Y10932D01*
X-1840Y11032D01*
X-1540D01*
Y11232D02*
X-1940D01*
Y11332D01*
X-1840Y11432D01*
X-1540D01*
X-1840D01*
X-1940Y11532D01*
X-1840Y11632D01*
X-1540D01*
D17*
X15612Y10013D02*
D03*
X15218D02*
D03*
X14825D02*
D03*
X14431D02*
D03*
X14037D02*
D03*
X13644D02*
D03*
X13250D02*
D03*
X12856D02*
D03*
X12463D02*
D03*
X12069D02*
D03*
X11675D02*
D03*
X11281D02*
D03*
X10888D02*
D03*
X10494D02*
D03*
X15612Y9619D02*
D03*
X15218D02*
D03*
X14825D02*
D03*
X14431D02*
D03*
X14037D02*
D03*
X13644D02*
D03*
X13250D02*
D03*
X12856D02*
D03*
X12463D02*
D03*
X12069D02*
D03*
X11675D02*
D03*
X11281D02*
D03*
X10888D02*
D03*
X10494D02*
D03*
X15609Y9241D02*
D03*
X15216D02*
D03*
X14822D02*
D03*
X14428D02*
D03*
X14035D02*
D03*
X13641D02*
D03*
X13247D02*
D03*
X12854D02*
D03*
X12460D02*
D03*
X12066D02*
D03*
X11672D02*
D03*
X11279D02*
D03*
X10885D02*
D03*
X10491D02*
D03*
X15612Y8831D02*
D03*
X15218D02*
D03*
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16
Project Outputs for Pcie_Brige_Test/PcieBrige-ASM/Pick Place for PCIE_Brige_PCB.csv Normal file
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Altium Designer Pick and Place Locations
C:\Users\qp\Documents\Pcie_Brige_Test\Project Outputs for Pcie_Brige_Test\Pick Place for PCIE_Brige_PCB.csv
========================================================================================================================
File Design Information:
Date: 22/11/22
Time: 17:26
Revision: 676086060d45bb250d5119337dd77fa032be809e
Variant: No variations
Units used: mil
"Designator","Comment","Layer","Footprint","Center-X(mil)","Center-Y(mil)","Rotation"
"U1","PI7C9X2G608GP","TopLayer","BGA196","1305.176mil","1020.945mil","180"
"R2","1.43K¦¸ (1431) ¡À1%","TopLayer","LC-0402_R","1288.386mil","669.291mil","0"
"R1","1.43K¦¸ (1431) ¡À1%","TopLayer","LC-0402_R","1342.520mil","1370.079mil","0"
Can't render this file because it has a wrong number of fields in line 13.

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0
Project Outputs for Pcie_Brige_Test/PcieBrige-CAM/PCIE_Brige_PCB-macro.APR_LIB Normal file
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18
Project Outputs for Pcie_Brige_Test/PcieBrige-CAM/PCIE_Brige_PCB.DRR Normal file
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----------------------------------------------------------------------------------------------------------------------------------
NCDrill File Report For: PCIE_Brige_PCB.PcbDoc 2022/11/22 17:26:18
----------------------------------------------------------------------------------------------------------------------------------
Layer Pair : Top Layer to Bottom Layer
ASCII RoundHoles File : PCIE_Brige_PCB.TXT
Tool Hole Size Hole Tolerance Hole Type Hole Count Plated Tool Travel
----------------------------------------------------------------------------------------------------------------------------------
T1 12mil (0.3mm) Round 68 PTH 9.21inch (233.96mm)
T2 24mil (0.599mm) Round 40 PTH 4.87inch (123.73mm)
T3 32mil (0.8mm) Round 32 PTH 7.95inch (201.90mm)
T4 35mil (0.899mm) Round 32 PTH 6.87inch (174.48mm)
T5 138mil (3.5mm) Round 4 PTH 5.91inch (150.09mm)
----------------------------------------------------------------------------------------------------------------------------------
Totals 176
Total Processing Time (hh:mm:ss) : 00:00:00

22
Project Outputs for Pcie_Brige_Test/PcieBrige-CAM/PCIE_Brige_PCB.EXTREP Normal file
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------------------------------------------------------------------------------------------
Gerber File Extension Report For: PCIE_Brige_PCB.GBR 2022/11/22 17:25:24
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
Layer Extension Layer Description
------------------------------------------------------------------------------------------
.GTO Top Overlay
.GTP Top Paste
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.GTL Top Layer
.GP1 GND02
.GP2 VCC03
.GBL Bottom Layer
.GBS Bottom Solder
.GBP Bottom Paste
.GBO Bottom Overlay
.GM1 Mechanical 1
.GD1 Drill Drawing
.GG1 Drill Guide
------------------------------------------------------------------------------------------

2800
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1560
Project Outputs for Pcie_Brige_Test/PcieBrige-CAM/PCIE_Brige_PCB.GD1 Normal file
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Project Outputs for Pcie_Brige_Test/PcieBrige-CAM/PCIE_Brige_PCB.GG1 Normal file
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M02*

344
Project Outputs for Pcie_Brige_Test/PcieBrige-CAM/PCIE_Brige_PCB.GM1 Normal file
View File

@ -0,0 +1,344 @@
G04*
G04 #@! TF.GenerationSoftware,Altium Limited,Altium Designer,22.0.2 (36)*
G04*
G04 Layer_Color=16711935*
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G70*
G04*
G04 #@! TF.SameCoordinates,CD407462-B920-417C-8B87-A3646CBED1B3*
G04*
G04*
G04 #@! TF.FilePolarity,Positive*
G04*
G01*
G75*
%ADD11C,0.0100*%
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D11*
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M02*

432
Project Outputs for Pcie_Brige_Test/PcieBrige-CAM/PCIE_Brige_PCB.GP1 Normal file
View File

@ -0,0 +1,432 @@
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G04 #@! TF.GenerationSoftware,Altium Limited,Altium Designer,22.0.2 (36)*
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X25591Y-1850D02*
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546
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5351
Project Outputs for Pcie_Brige_Test/PcieBrige-CAM/PCIE_Brige_PCB.GTL Normal file
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22760
Project Outputs for Pcie_Brige_Test/PcieBrige-CAM/PCIE_Brige_PCB.GTO Normal file
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628
Project Outputs for Pcie_Brige_Test/PcieBrige-CAM/PCIE_Brige_PCB.GTP Normal file
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@ -0,0 +1,628 @@
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Project Outputs for Pcie_Brige_Test/PcieBrige-CAM/PCIE_Brige_PCB.GTS Normal file
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D03*
X11772D02*
D03*
X12772D02*
D03*
X13772D02*
D03*
X7618Y4173D02*
D03*
X6618D02*
D03*
X18996Y4114D02*
D03*
X17996D02*
D03*
X2050Y12350D02*
D03*
Y13350D02*
D03*
Y14350D02*
D03*
X2008Y8079D02*
D03*
Y9079D02*
D03*
X16950Y16650D02*
D03*
X17950D02*
D03*
X18950D02*
D03*
X19950D02*
D03*
D23*
X7008Y8650D02*
D03*
Y10020D02*
D03*
Y6100D02*
D03*
Y7400D02*
D03*
Y10780D02*
D03*
Y12000D02*
D03*
Y13260D02*
D03*
Y14488D02*
D03*
X4469Y10228D02*
D03*
D24*
X7008Y8150D02*
D03*
X13750Y4028D02*
D03*
X10059D02*
D03*
X11319D02*
D03*
X12550D02*
D03*
X15000D02*
D03*
X16200D02*
D03*
X23631Y2953D02*
D03*
X22936Y2664D02*
D03*
X22647Y1969D02*
D03*
X22936Y1273D02*
D03*
X23631Y984D02*
D03*
X24327Y1273D02*
D03*
Y2664D02*
D03*
X24616Y1969D02*
D03*
X2953D02*
D03*
X2664Y2664D02*
D03*
Y1273D02*
D03*
X1969Y984D02*
D03*
X1273Y1273D02*
D03*
X984Y1969D02*
D03*
X1273Y2664D02*
D03*
X1969Y2953D02*
D03*
X2953Y17731D02*
D03*
X2664Y18427D02*
D03*
Y17036D02*
D03*
X1969Y16747D02*
D03*
X1273Y17036D02*
D03*
X984Y17731D02*
D03*
X1273Y18427D02*
D03*
X1969Y18716D02*
D03*
X23631D02*
D03*
X22936Y18427D02*
D03*
X22647Y17731D02*
D03*
X22936Y17036D02*
D03*
X23631Y16747D02*
D03*
X24327Y17036D02*
D03*
Y18427D02*
D03*
X24616Y17731D02*
D03*
X7008Y9520D02*
D03*
Y5600D02*
D03*
Y6900D02*
D03*
Y11280D02*
D03*
Y12500D02*
D03*
Y13760D02*
D03*
Y14988D02*
D03*
X4469Y10728D02*
D03*
X13050Y16500D02*
D03*
X15550D02*
D03*
X14300D02*
D03*
X12300D02*
D03*
X11050D02*
D03*
D25*
X23800Y6100D02*
D03*
X2050Y11350D02*
D03*
X2008Y10079D02*
D03*
D26*
X14772Y1339D02*
D03*
X8618Y4173D02*
D03*
X19996Y4114D02*
D03*
X20950Y16650D02*
D03*
D27*
X13250Y4028D02*
D03*
X9559D02*
D03*
X10819D02*
D03*
X12050D02*
D03*
X14500D02*
D03*
X15700D02*
D03*
X13550Y16500D02*
D03*
X16050D02*
D03*
X14800D02*
D03*
X11800D02*
D03*
X10550D02*
D03*
D28*
X23631Y1969D02*
D03*
X1969D02*
D03*
Y17731D02*
D03*
X23631D02*
D03*
M02*

2
Project Outputs for Pcie_Brige_Test/PcieBrige-CAM/PCIE_Brige_PCB.LDP Normal file
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@ -0,0 +1,2 @@
Layer Pairs Export File for PCB: C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
LayersSetName=Top_Bot_Thru_Holes|DrillFile=pcie_brige_pcb.txt|DrillLayers=gtl,gp1,gp2,gbl

294
Project Outputs for Pcie_Brige_Test/PcieBrige-CAM/PCIE_Brige_PCB.REP Normal file
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@ -0,0 +1,294 @@
*************************************************************
FileName = PCIE_Brige_PCB.GBR
AutoAperture = True
*************************************************************
Generating : Top Layer
File : PCIE_Brige_PCB.GTL
Adding Layer : Top Layer
Adding Layer : Mechanical 1
Adding Layer : Multi-Layer
Used DCodes :
D11
D14
D15
D16
D17
D18
D19
D29
D30
D31
D32
D33
D34
D35
D36
*************************************************************
*************************************************************
Generating : GND02
File : PCIE_Brige_PCB.GP1
Adding Layer : GND02
Adding Layer : Mechanical 1
Adding Layer : Multi-Layer
Used DCodes :
D11
D14
D15
D16
D37
D38
D39
D40
*************************************************************
*************************************************************
Generating : VCC03
File : PCIE_Brige_PCB.GP2
Adding Layer : VCC03
Adding Layer : Mechanical 1
Adding Layer : Multi-Layer
Used DCodes :
D11
D14
D15
D16
D37
D38
D39
D40
D41
D42
*************************************************************
*************************************************************
Generating : Bottom Layer
File : PCIE_Brige_PCB.GBL
Adding Layer : Bottom Layer
Adding Layer : Mechanical 1
Adding Layer : Multi-Layer
Used DCodes :
D11
D14
D15
D16
D19
D29
D30
D31
D32
D33
D34
D35
D36
*************************************************************
*************************************************************
Generating : Bottom Paste
File : PCIE_Brige_PCB.GBP
Adding Layer : Bottom Paste
Adding Layer : Mechanical 1
Adding Layer : Bottom Layer
Adding Layer : Multi-Layer
Used DCodes :
D11
D14
D15
D16
*************************************************************
*************************************************************
Generating : Mechanical 1
File : PCIE_Brige_PCB.GM1
Adding Layer : Mechanical 1
Adding Layer : Mechanical 1
Used DCodes :
D11
D14
D15
D16
*************************************************************
*************************************************************
Generating : Bottom Overlay
File : PCIE_Brige_PCB.GBO
Adding Layer : Bottom Overlay
Adding Layer : Mechanical 1
Used DCodes :
D11
D14
D15
D16
*************************************************************
*************************************************************
Generating : Top Overlay
File : PCIE_Brige_PCB.GTO
Adding Layer : Top Overlay
Adding Layer : Mechanical 1
Used DCodes :
D10
D11
D12
D13
D14
D15
D16
*************************************************************
*************************************************************
Generating : Top Paste
File : PCIE_Brige_PCB.GTP
Adding Layer : Top Paste
Adding Layer : Mechanical 1
Adding Layer : Top Layer
Adding Layer : Multi-Layer
Used DCodes :
D11
D14
D15
D16
D17
D18
D19
*************************************************************
*************************************************************
Generating : Top Solder
File : PCIE_Brige_PCB.GTS
Adding Layer : Top Solder
Adding Layer : Mechanical 1
Adding Layer : Top Layer
Adding Layer : Multi-Layer
Used DCodes :
D11
D14
D15
D16
D20
D21
D22
D23
D24
D25
D26
D27
D28
*************************************************************
*************************************************************
Generating : Bottom Solder
File : PCIE_Brige_PCB.GBS
Adding Layer : Bottom Solder
Adding Layer : Mechanical 1
Adding Layer : Bottom Layer
Adding Layer : Multi-Layer
Used DCodes :
D11
D14
D15
D16
D22
D23
D24
D25
D26
D27
D28
*************************************************************
*************************************************************
Generating : Drill Drawing
File : PCIE_Brige_PCB.GD1
Adding Layer : Mechanical 1
Adding Drill Pair : Top Layer-Bottom Layer
Adding Layer : Drill Drawing
Used DCodes :
D11
D14
D15
D16
D43
D44
*************************************************************
*************************************************************
Generating : Drill Guide
File : PCIE_Brige_PCB.GG1
Adding Layer : Mechanical 1
Adding Drill Pair : Top Layer-Bottom Layer
Adding Layer : Drill Guide
Used DCodes :
D11
D14
D15
D16
D43
*************************************************************

5
Project Outputs for Pcie_Brige_Test/PcieBrige-CAM/PCIE_Brige_PCB.RUL Normal file
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DRC Rules Export File for PCB: C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=4.00
RuleKind=Width|RuleName=Width|Scope=Board|Minimum=4.00
RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=6.00
RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0

193
Project Outputs for Pcie_Brige_Test/PcieBrige-CAM/PCIE_Brige_PCB.TXT Normal file
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M48
;Layer_Color=9474304
;FILE_FORMAT=2:4
INCH,LZ
;TYPE=PLATED
T1F00S00C0.0118
T2F00S00C0.0236
T3F00S00C0.0315
T4F00S00C0.0354
T5F00S00C0.1378
%
T01
X021142Y009508
X023071Y008091
X02315Y012067
X01939Y011437
X016929Y011417
X015394Y011811
X015
X014622Y011859
X014218Y011758
X014667Y011378
Y010984
Y01061
X014825Y010406
X014626Y010197
X013839
Y010551
X013425
Y010197
Y009823
Y009429
X013839
Y009823
Y010984
X013425
X012657
X012264
Y010571
Y010197
Y009823
X012657
Y010197
Y010571
Y009409
X012264
X011473Y009397
X011437Y009055
X011083Y008661
X010689Y008268
X010394Y007343
X009803Y007756
X010591Y006358
X012069Y008438
X013644
X014272Y008672
X014626Y008268
X015Y009055
Y009429
X013051Y009075
X011102Y009823
X011476Y010217
X011496Y010591
X011281Y0108
X011083Y011004
Y011398
X011102Y011772
X010494Y011981
X012069
X012264Y011791
X012997Y011729
X013445Y012185
X016949Y003484
X017205Y003031
X005157Y006496
Y007539
X010276Y013386
X016929Y015935
X017953
X020965Y015925
T02
X007008Y0056
Y0061
Y0069
Y0074
Y00815
Y00865
Y00952
Y01002
Y01078
Y01128
Y012
Y0125
X004469Y010728
Y010228
X009559Y004028
X010059
X010819
X011319
X01205
X01255
X01325
X01375
X0145
X015
X0157
X0162
X01605Y0165
X01555
X0148
X0143
X01355
X01305
X0123
X0118
X01105
X01055
X007008Y014988
Y014488
Y01376
Y01326
T03
X022936Y001273
X022647Y001969
X022936Y002664
X023631Y002953
X024327Y002664
X024616Y001969
X024327Y001273
X023631Y000984
X002664Y001273
X002953Y001969
X002664Y002664
X001969Y002953
X001273Y002664
X000984Y001969
X001273Y001273
X001969Y000984
Y016747
X002664Y017036
X002953Y017731
X002664Y018427
X001969Y018716
X001273Y018427
X000984Y017731
X001273Y017036
X022936
X022647Y017731
X022936Y018427
X023631Y018716
X024327Y018427
X024616Y017731
X024327Y017036
X023631Y016747
T04
X018996Y004114
X019996
X0238Y0061
Y0071
Y0081
Y0091
Y0101
Y0111
Y0121
Y0131
X017996Y004114
X014772Y001339
X013772
X012772
X011772
X010772
X009772
X008618Y004173
X007618
X006618
X002008Y008079
Y009079
Y010079
X00205Y01135
Y01235
Y01335
Y01435
X01695Y01665
X01795
X01895
X01995
X02095
T05
X023631Y001969
X001969
Y017731
X023631
M30

35
Project Outputs for Pcie_Brige_Test/PcieBrige-CAM/PCIE_Brige_PCB.apr Normal file
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D10 ROUNDED 15.748 15.748 0.000 LINE 0.000
D11 ROUNDED 10.000 10.000 0.000 LINE 0.000
D12 ROUNDED 3.937 3.937 0.000 LINE 0.000
D13 ROUNDED 7.874 7.874 0.000 LINE 0.000
D14 ROUNDED 19.685 19.685 0.000 LINE 0.000
D15 ROUNDED 9.842 9.842 0.000 LINE 0.000
D16 ROUNDED 6.000 6.000 0.000 LINE 0.000
D17 ROUNDED 13.780 13.780 0.000 FLASH 0.000
D18 RECTANGULAR 23.622 25.591 0.000 FLASH 0.000
D19 ROUNDED 59.055 59.055 0.000 FLASH 0.000
D20 ROUNDED 21.779 21.779 0.000 FLASH 0.000
D21 RECTANGULAR 27.622 29.591 0.000 FLASH 0.000
D22 ROUNDED 67.055 67.055 0.000 FLASH 0.000
D23 RECTANGULAR 47.370 47.370 0.000 FLASH 270.000
D24 ROUNDED 47.370 47.370 0.000 FLASH 0.000
D25 RECTANGULAR 67.055 67.055 0.000 FLASH 90.000
D26 RECTANGULAR 67.055 67.055 0.000 FLASH 180.000
D27 RECTANGULAR 47.370 47.370 0.000 FLASH 0.000
D28 ROUNDED 283.591 283.591 0.000 FLASH 0.000
D29 RECTANGULAR 39.370 39.370 0.000 FLASH 270.000
D30 ROUNDED 39.370 39.370 0.000 FLASH 0.000
D31 RECTANGULAR 59.055 59.055 0.000 FLASH 90.000
D32 RECTANGULAR 59.055 59.055 0.000 FLASH 180.000
D33 RECTANGULAR 39.370 39.370 0.000 FLASH 0.000
D34 ROUNDED 275.591 275.591 0.000 FLASH 0.000
D35 ROUNDED 17.716 17.716 0.000 FLASH 0.000
D36 ROUNDED 19.685 19.685 0.000 FLASH 0.000
D37 ROUNDED 40.000 40.000 0.000 LINE 0.000
D38 ROUNDED 39.622 39.622 0.000 FLASH 0.000
D39 ROUNDED 51.433 51.433 0.000 FLASH 0.000
D40 ROUNDED 27.811 27.811 0.000 FLASH 0.000
D41 ROUNDED 153.795 153.795 0.000 FLASH 0.000
D42 ROUNDED 47.496 47.496 0.000 FLASH 0.000
D43 ROUNDED 2.000 2.000 0.000 LINE 0.000
D44 ROUNDED 2.667 2.667 0.000 LINE 0.000

BIN
Project Outputs for Pcie_Brige_Test/PcieBrige-CAM/Pcie_Brige_Test_ASM.pdf Normal file
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Binary file not shown.

16
Project Outputs for Pcie_Brige_Test/PcieBrige-CAM/Pick Place for PCIE_Brige_PCB.csv Normal file
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Altium Designer Pick and Place Locations
C:\Users\qp\Documents\Pcie_Brige_Test\Project Outputs for Pcie_Brige_Test\Pick Place for PCIE_Brige_PCB.csv
========================================================================================================================
File Design Information:
Date: 22/11/22
Time: 17:26
Revision: 676086060d45bb250d5119337dd77fa032be809e
Variant: No variations
Units used: mil
"Designator","Comment","Layer","Footprint","Center-X(mil)","Center-Y(mil)","Rotation"
"U1","PI7C9X2G608GP","TopLayer","BGA196","1305.176mil","1020.945mil","180"
"R2","1.43K¦¸ (1431) ¡À1%","TopLayer","LC-0402_R","1288.386mil","669.291mil","0"
"R1","1.43K¦¸ (1431) ¡À1%","TopLayer","LC-0402_R","1342.520mil","1370.079mil","0"
Can't render this file because it has a wrong number of fields in line 13.

66
Project Outputs for Pcie_Brige_Test/PcieBrige-CAM/Pick Place for PCIE_Brige_PCB.txt Normal file
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Altium Designer Pick and Place Locations
C:\Users\qp\Documents\Pcie_Brige_Test\Project Outputs for Pcie_Brige_Test\Pick Place for PCIE_Brige_PCB.txt
========================================================================================================================
File Design Information:
Date: 22/11/22
Time: 16:17
Revision: 676086060d45bb250d5119337dd77fa032be809e
Variant: No variations
Units used: mil
Designator Comment Layer Footprint Center-X(mil) Center-Y(mil) Rotation
H4 PlatedThrHole TopLayer PLATEDTHRHOLE 196.850 196.850 0
H3 PlatedThrHole TopLayer PLATEDTHRHOLE 2363.150 196.850 0
H2 PlatedThrHole TopLayer PLATEDTHRHOLE 196.850 1773.150 0
H1 PlatedThrHole TopLayer PLATEDTHRHOLE 2363.150 1773.150 0
U1 P17C9X2G608GP TopLayer BGA196 1305.176 1020.945 180
TPU6 A14 TopLayer TESTPOINT 435.039 651.575 90
TPU5 B14 TopLayer TESTPOINT 437.008 753.937 90
TPU4 M13 TopLayer TESTPOINT 484.252 1789.370 90
TPU3 P14 TopLayer TESTPOINT 694.882 1789.370 90
TPU2 L1 TopLayer TESTPOINT 1877.953 1238.189 90
TPU1 J12 TopLayer TESTPOINT 592.520 1789.370 90
TPD11 P13 TopLayer TESTPOINT 899.606 1789.370 90
TPD10 N13 TopLayer TESTPOINT 801.181 1789.370 90
TPD9 J2 TopLayer TESTPOINT 1877.953 1141.732 90
TPD8 L2 TopLayer TESTPOINT 2000.000 1240.158 90
TPD7 G2 TopLayer TESTPOINT 1753.937 1013.779 90
TPD6 H2 TopLayer TESTPOINT 1877.953 1017.716 90
TPD5 F3 TopLayer TESTPOINT 2112.205 1015.748 90
TPD4 F1 TopLayer TESTPOINT 2000.000 1013.779 90
TPD3 G3 TopLayer TESTPOINT 2000.000 1147.638 90
TPD2 J3 TopLayer TESTPOINT 1753.937 1143.701 90
TPD1 G2 TopLayer TESTPOINT 1753.937 1240.158 90
TP2 C2 TopLayer TESTPOINT 2003.937 610.236 0
TP1 B1 TopLayer TESTPOINT 2003.937 519.685 0
R2 "1.43K¦¸ (1431) ¡À1%" TopLayer LC-0402_R 1288.386 669.291 0
R1 "1.43K¦¸ (1431) ¡À1%" TopLayer LC-0402_R 1342.520 1370.079 0
P28 VCC TopLayer HDR1X6 1227.165 133.858 180
P26 CLKREQ4-6 TopLayer HDR1X3 1899.606 411.417 180
P25 CLKREQ1_3 TopLayer HDR1X3 200.787 907.874 270
P24 GPIO TopLayer HDR1X8 2380.000 960.000 90
P23 SHPC TopLayer HDR1X3 761.811 417.323 180
P22 E2PROM TopLayer HDR1X4 205.000 1285.000 90
P21 I2C/J11/F12 TopLayer MHDR1X2 446.850 1047.835 90
P20 PER7 TopLayer MHDR1X2 1595.000 402.756 0
P19 PER6 TopLayer MHDR1X2 1475.000 402.756 0
P18 PER5 TopLayer MHDR1X2 1230.000 402.756 0
P17 PER4 TopLayer MHDR1X2 1106.890 402.756 0
P16 REFCLK_O7 TopLayer MHDR1X2 700.787 1473.819 90
P15 REFCLK_O6 TopLayer MHDR1X2 700.787 1350.984 90
P14 REFCLK_O5 TopLayer MHDR1X2 700.787 1225.000 90
P13 REFCLK_O4 TopLayer MHDR1X2 700.787 1102.953 90
P12 DWNRST TopLayer HDR1X5 1895.000 1665.000 180
P11 C12/E12 TopLayer MHDR1X2 980.905 402.756 0
P10 REFCLK1 TopLayer MHDR1X2 1350.000 402.756 0
P9 REFCLK0 TopLayer MHDR1X2 1330.000 1650.000 180
P8 PER4 TopLayer MHDR1X2 1080.000 1650.000 0
P7 PER3 TopLayer MHDR1X2 1205.000 1650.000 0
P6 PER2 TopLayer MHDR1X2 1455.000 1650.000 180
P5 PER1 TopLayer MHDR1X2 1580.000 1650.000 180
P4 REFCLK_O3 TopLayer MHDR1X2 700.787 840.000 270
P3 REFCLK_O2 TopLayer MHDR1X2 700.787 715.000 270
P2 REFCLK_O1 TopLayer MHDR1X2 700.787 585.000 270
P1 REFCLK_I TopLayer MHDR1X2 700.787 976.968 270

25
Project Outputs for Pcie_Brige_Test/PcieBrige-CAM/Status Report.Txt Normal file
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Output: Gerber Files
Type : Gerber
From : Variant [[No Variations]] of Project [Pcie_Brige_Test.PrjPcb]
Generated File[PCIE_Brige_PCB.GTO]
Generated File[PCIE_Brige_PCB.GTP]
Generated File[PCIE_Brige_PCB.GTS]
Generated File[PCIE_Brige_PCB.GTL]
Generated File[PCIE_Brige_PCB.GP1]
Generated File[PCIE_Brige_PCB.GP2]
Generated File[PCIE_Brige_PCB.GBL]
Generated File[PCIE_Brige_PCB.GBS]
Generated File[PCIE_Brige_PCB.GBP]
Generated File[PCIE_Brige_PCB.GBO]
Generated File[PCIE_Brige_PCB.GM1]
Generated File[PCIE_Brige_PCB.GD1]
Generated File[PCIE_Brige_PCB.GG1]
Generated File[PCIE_Brige_PCB.RUL]
Generated File[PCIE_Brige_PCB.EXTREP]
Generated File[PCIE_Brige_PCB.REP]
Files Generated : 16
Documents Printed : 0
Finished Output Generation At 16:14:31 On 2022/11/22

BIN
Project Outputs for Pcie_Brige_Test/Pcie_Brige_Test_ASM.pdf Normal file
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Binary file not shown.

16
Project Outputs for Pcie_Brige_Test/Pick Place for PCIE_Brige_PCB.csv Normal file
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Altium Designer Pick and Place Locations
C:\Users\qp\Documents\Pcie_Brige_Test\Project Outputs for Pcie_Brige_Test\Pick Place for PCIE_Brige_PCB.csv
========================================================================================================================
File Design Information:
Date: 22/11/22
Time: 17:26
Revision: 676086060d45bb250d5119337dd77fa032be809e
Variant: No variations
Units used: mil
"Designator","Comment","Layer","Footprint","Center-X(mil)","Center-Y(mil)","Rotation"
"U1","PI7C9X2G608GP","TopLayer","BGA196","1305.176mil","1020.945mil","180"
"R2","1.43K¦¸ (1431) ¡À1%","TopLayer","LC-0402_R","1288.386mil","669.291mil","0"
"R1","1.43K¦¸ (1431) ¡À1%","TopLayer","LC-0402_R","1342.520mil","1370.079mil","0"
Can't render this file because it has a wrong number of fields in line 13.

10
Project Outputs for Pcie_Brige_Test/Status Report.Txt Normal file
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@ -0,0 +1,10 @@
Output: Generates pick and place files
Type : Pick Place
From : Variant [[No Variations]] of Project [Pcie_Brige_Test.PrjPcb]
Generated File[Pick Place for PCIE_Brige_PCB.csv]
Files Generated : 1
Documents Printed : 0
Finished Output Generation At 17:26:45 On 2022/11/22

6
__Previews/Pcie_Brige_Cfg.SchDocPreview
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6
__Previews/Pcie_Brige_Core.SchDocPreview
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6
__Previews/Pcie_Brige_pwr.SchDocPreview
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pcie_test.SchLib
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