47 lines
3.0 KiB
Plaintext
47 lines
3.0 KiB
Plaintext
Removed Pin From Net: NetName=CLKREQ_L6 Pin=P25-4
|
|
Removed Pin From Net: NetName=CLKREQ_L5 Pin=P25-5
|
|
Removed Pin From Net: NetName=CLKREQ_L4 Pin=P25-6
|
|
Removed Member From Class: ClassName=Pcie_Brige_Core Member=P21
|
|
Removed Member From Class: ClassName=Pcie_Brige_Core Member=P22
|
|
Removed Member From Class: ClassName=Pcie_Brige_Core Member=P23
|
|
Removed Member From Class: ClassName=Pcie_Brige_Core Member=P24
|
|
Removed Member From Class: ClassName=Pcie_Brige_Cfg Member=P25
|
|
Removed Member From Class: ClassName=Pcie_Brige_Core Member=P25
|
|
Removed Member From Class: ClassName=Pcie_Brige_Core Member=P26
|
|
Removed Member From Class: ClassName=Pcie_Brige_Core Member=P27
|
|
Added Component: Designator=P28(HDR1X3)
|
|
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
|
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
|
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
|
Added Component: Designator=P29(HDR1X3)
|
|
Add component (AddParameter): Name = "LatestRevisionDate"; Value = "17-Jul-2002"; VariantName = "[No Variations]"
|
|
Add component (AddParameter): Name = "LatestRevisionNote"; Value = "Re-released for DXP Platform."; VariantName = "[No Variations]"
|
|
Add component (AddParameter): Name = "Publisher"; Value = "Altium Limited"; VariantName = "[No Variations]"
|
|
Added Pin To Net: NetName=CLKREQ_L6 Pin=P28-1
|
|
Added Pin To Net: NetName=CLKREQ_L5 Pin=P28-2
|
|
Added Pin To Net: NetName=CLKREQ_L4 Pin=P28-3
|
|
Added Pin To Net: NetName=PCIE_SW_VDDR_3V3 Pin=U1-D14
|
|
Added Pin To Net: NetName=CLKREQ_L1 Pin=P29-1
|
|
Added Pin To Net: NetName=CLKREQ_L1 Pin=U1-F11
|
|
Added Net: Name=CLKREQ_L1
|
|
Added Pin To Net: NetName=CLKREQ_L2 Pin=P29-2
|
|
Added Pin To Net: NetName=CLKREQ_L2 Pin=U1-D12
|
|
Added Net: Name=CLKREQ_L2
|
|
Added Pin To Net: NetName=CLKREQ_L3 Pin=P29-3
|
|
Added Pin To Net: NetName=CLKREQ_L3 Pin=U1-C13
|
|
Added Net: Name=CLKREQ_L3
|
|
Added Member To Class: ClassName=Pcie_Brige_Core Member=Component P1 REFCLK_I
|
|
Added Member To Class: ClassName=Pcie_Brige_Core Member=Component P2 REFCLK_O1
|
|
Added Member To Class: ClassName=Pcie_Brige_Core Member=Component P5 PER1
|
|
Added Member To Class: ClassName=Pcie_Brige_Core Member=Component P6 PER2
|
|
Added Member To Class: ClassName=Pcie_Brige_Core Member=Component P7 PER3
|
|
Added Member To Class: ClassName=Pcie_Brige_Core Member=Component P8 PER4
|
|
Added Member To Class: ClassName=Pcie_Brige_Core Member=Component P9 REFCLK0
|
|
Added Member To Class: ClassName=Pcie_Brige_Core Member=Component P11 C12/E12
|
|
Added Member To Class: ClassName=Pcie_Brige_Core Member=Component P14 REFCLK_O5
|
|
Added Member To Class: ClassName=Pcie_Brige_Core Member=Component P15 REFCLK_O6
|
|
Added Member To Class: ClassName=Pcie_Brige_Core Member=Component P16 REFCLK_O7
|
|
Added Member To Class: ClassName=Pcie_Brige_Core Member=Component P17 PER4
|
|
Added Member To Class: ClassName=Pcie_Brige_Cfg Member=Component P28 CLKREQ4-6
|
|
Added Member To Class: ClassName=Pcie_Brige_Cfg Member=Component P29 CLKREQ1_3
|