| .. |
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Manufactory
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Test product V.01
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2022-11-22 17:46:08 +08:00 |
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PCIE_Brige_PCB.~(1).PcbDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
PCIE_Brige_PCB.~(2).PcbDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
PCIE_Brige_PCB.~(3).PcbDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
PCIE_Brige_PCB.~(4).PcbDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
PCIE_Brige_PCB.~(5).PcbDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
PCIE_Brige_PCB.~(6).PcbDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
PCIE_Brige_PCB.~(7).PcbDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
PCIE_Brige_PCB.~(8).PcbDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
PCIE_Brige_PCB.~(9).PcbDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
PCIE_Brige_PCB.~(10).PcbDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
PCIE_Brige_PCB.~(11).PcbDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
PCIE_Brige_PCB.~(12).PcbDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
PCIE_Brige_PCB.~(13).PcbDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
PCIE_Brige_PCB.~(14).PcbDoc.Zip
|
PCB布局完成
|
2022-11-21 00:54:03 +08:00 |
|
PCIE_Brige_PCB.~(15).PcbDoc.Zip
|
PCB布局完成
|
2022-11-21 00:54:03 +08:00 |
|
PCIE_Brige_PCB.~(16).PcbDoc.Zip
|
PCB布局完成
|
2022-11-21 00:54:03 +08:00 |
|
PCIE_Brige_PCB.~(17).PcbDoc.Zip
|
PCB布局完成
|
2022-11-21 00:54:03 +08:00 |
|
PCIE_Brige_PCB.~(18).PcbDoc.Zip
|
PCB布局完成
|
2022-11-21 00:54:03 +08:00 |
|
PCIE_Brige_PCB.~(19).PcbDoc.Zip
|
PCB布局完成
|
2022-11-21 00:54:03 +08:00 |
|
PCIE_Brige_PCB.~(20).PcbDoc.Zip
|
PCB布局完成
|
2022-11-21 00:54:03 +08:00 |
|
PCIE_Brige_PCB.~(21).PcbDoc.Zip
|
第一次布线完成
|
2022-11-21 13:17:30 +08:00 |
|
PCIE_Brige_PCB.~(22).PcbDoc.Zip
|
第一次布线完成
|
2022-11-21 13:17:30 +08:00 |
|
PCIE_Brige_PCB.~(23).PcbDoc.Zip
|
第一次布线完成
|
2022-11-21 13:17:30 +08:00 |
|
PCIE_Brige_PCB.~(24).PcbDoc.Zip
|
第一次布线完成
|
2022-11-21 13:17:30 +08:00 |
|
PCIE_Brige_PCB.~(25).PcbDoc.Zip
|
第一次布线完成
|
2022-11-21 13:17:30 +08:00 |
|
PCIE_Brige_PCB.~(26).PcbDoc.Zip
|
第一次布线完成
|
2022-11-21 13:17:30 +08:00 |
|
PCIE_Brige_PCB.~(27).PcbDoc.Zip
|
第一次布线完成
|
2022-11-21 13:17:30 +08:00 |
|
PCIE_Brige_PCB.~(28).PcbDoc.Zip
|
第一次布线完成
|
2022-11-21 13:17:30 +08:00 |
|
PCIE_Brige_PCB.~(29).PcbDoc.Zip
|
第一次布线完成
|
2022-11-21 13:17:30 +08:00 |
|
PCIE_Brige_PCB.~(30).PcbDoc.Zip
|
重新设置最小间距为6mil
|
2022-11-21 17:10:20 +08:00 |
|
PCIE_Brige_PCB.~(31).PcbDoc.Zip
|
重新设置最小间距为6mil
|
2022-11-21 17:10:20 +08:00 |
|
PCIE_Brige_PCB.~(32).PcbDoc.Zip
|
重新设置最小间距为6mil
|
2022-11-21 17:10:20 +08:00 |
|
PCIE_Brige_PCB.~(33).PcbDoc.Zip
|
重新设置最小间距为6mil
|
2022-11-21 17:10:20 +08:00 |
|
PCIE_Brige_PCB.~(34).PcbDoc.Zip
|
重新设置最小间距为6mil
|
2022-11-21 17:10:20 +08:00 |
|
PCIE_Brige_PCB.~(35).PcbDoc.Zip
|
铺铜完成，修正过孔覆盖绿油
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2022-11-21 20:39:38 +08:00 |
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PCIE_Brige_PCB.~(36).PcbDoc.Zip
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铺铜完成，修正过孔覆盖绿油
|
2022-11-21 20:39:38 +08:00 |
|
PCIE_Brige_PCB.~(37).PcbDoc.Zip
|
铺铜完成，修正过孔覆盖绿油
|
2022-11-21 20:39:38 +08:00 |
|
PCIE_Brige_PCB.~(38).PcbDoc.Zip
|
铺铜完成，修正过孔覆盖绿油
|
2022-11-21 20:39:38 +08:00 |
|
PCIE_Brige_PCB.~(39).PcbDoc.Zip
|
铺铜完成，修正过孔覆盖绿油
|
2022-11-21 20:39:38 +08:00 |
|
PCIE_Brige_PCB.~(40).PcbDoc.Zip
|
铺铜完成，修正过孔覆盖绿油
|
2022-11-21 20:39:38 +08:00 |
|
PCIE_Brige_PCB.~(41).PcbDoc.Zip
|
铺铜完成，修正过孔覆盖绿油
|
2022-11-21 20:39:38 +08:00 |
|
PCIE_Brige_PCB.~(42).PcbDoc.Zip
|
铺铜完成，修正过孔覆盖绿油
|
2022-11-21 20:39:38 +08:00 |
|
PCIE_Brige_PCB.~(43).PcbDoc.Zip
|
铺铜完成，修正过孔覆盖绿油
|
2022-11-21 20:39:38 +08:00 |
|
PCIE_Brige_PCB.~(44).PcbDoc.Zip
|
铺铜完成，修正过孔覆盖绿油
|
2022-11-21 20:39:38 +08:00 |
|
PCIE_Brige_PCB.~(45).PcbDoc.Zip
|
铺铜完成，修正过孔覆盖绿油
|
2022-11-21 20:39:38 +08:00 |
|
PCIE_Brige_PCB.~(46).PcbDoc.Zip
|
铺铜完成，修正过孔覆盖绿油
|
2022-11-21 20:39:38 +08:00 |
|
PCIE_Brige_PCB.~(47).PcbDoc.Zip
|
铺铜完成，修正过孔覆盖绿油
|
2022-11-21 20:39:38 +08:00 |
|
PCIE_Brige_PCB.~(48).PcbDoc.Zip
|
铺铜完成，修正过孔覆盖绿油
|
2022-11-21 20:39:38 +08:00 |
|
PCIE_Brige_PCB.~(49).PcbDoc.Zip
|
DCT检查通过
|
2022-11-21 22:54:44 +08:00 |
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PCIE_Brige_PCB.~(50).PcbDoc.Zip
|
DCT检查通过
|
2022-11-21 22:54:44 +08:00 |
|
PCIE_Brige_PCB.~(51).PcbDoc.Zip
|
DCT检查通过
|
2022-11-21 22:54:44 +08:00 |
|
PCIE_Brige_PCB.~(52).PcbDoc.Zip
|
DCT检查通过
|
2022-11-21 22:54:44 +08:00 |
|
PCIE_Brige_PCB.~(53).PcbDoc.Zip
|
DCT检查通过
|
2022-11-21 22:54:44 +08:00 |
|
PCIE_Brige_PCB.~(54).PcbDoc.Zip
|
DCT检查通过
|
2022-11-21 22:54:44 +08:00 |
|
PCIE_Brige_PCB.~(55).PcbDoc.Zip
|
DCT检查通过
|
2022-11-21 22:54:44 +08:00 |
|
PCIE_Brige_PCB.~(56).PcbDoc.Zip
|
Test product V.01
|
2022-11-22 17:46:08 +08:00 |
|
PCIE_Brige_PCB.~(57).PcbDoc.Zip
|
Test product V.01
|
2022-11-22 17:46:08 +08:00 |
|
PCIE_Brige_PCB.~(58).PcbDoc.Zip
|
Test product V.01
|
2022-11-22 17:46:08 +08:00 |
|
PCIE_Brige_PCB.~(59).PcbDoc.Zip
|
Test product V.01
|
2022-11-22 17:46:08 +08:00 |
|
PCIE_Brige_PCB.~(60).PcbDoc.Zip
|
Test product V.01
|
2022-11-22 17:46:08 +08:00 |
|
PCIE_Brige_PCB.~(61).PcbDoc.Zip
|
Test product V.01
|
2022-11-22 17:46:08 +08:00 |
|
PCIE_Brige_PCB.~(62).PcbDoc.Zip
|
Test product V.01
|
2022-11-22 17:46:08 +08:00 |
|
Pcie_Brige_Borad.~(1).PcbDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Borad.~(2).PcbDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Borad.~(3).PcbDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Borad.~(4).PcbDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Borad.~(5).PcbDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Borad.~(6).PcbDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Borad.~(7).PcbDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Borad.~(8).PcbDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Borad.~(9).PcbDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Borad.~(10).PcbDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Borad.~(11).PcbDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Borad.~(12).PcbDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Borad.~(13).PcbDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Borad.~(14).PcbDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Borad.~(15).PcbDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Borad.~(16).PcbDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(1).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(2).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(3).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(4).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(5).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(6).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(7).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(8).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(9).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(10).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(11).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(12).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(13).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(14).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(15).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(16).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(17).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(18).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(19).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(20).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(21).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(22).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(23).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(24).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(25).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(26).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(27).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(28).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Cfg.~(29).SchDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
Pcie_Brige_Cfg.~(30).SchDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
Pcie_Brige_Cfg.~(31).SchDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
Pcie_Brige_Cfg.~(32).SchDoc.Zip
|
第一次布线完成
|
2022-11-21 13:17:30 +08:00 |
|
Pcie_Brige_Cfg.~(33).SchDoc.Zip
|
第一次布线完成
|
2022-11-21 13:17:30 +08:00 |
|
Pcie_Brige_Cfg.~(34).SchDoc.Zip
|
重新设置最小间距为6mil
|
2022-11-21 17:10:20 +08:00 |
|
Pcie_Brige_Cfg.~(35).SchDoc.Zip
|
重新设置最小间距为6mil
|
2022-11-21 17:10:20 +08:00 |
|
Pcie_Brige_Cfg.~(36).SchDoc.Zip
|
Test product V.01
|
2022-11-22 17:46:08 +08:00 |
|
Pcie_Brige_Cfg.~(37).SchDoc.Zip
|
Test product V.01
|
2022-11-22 17:46:08 +08:00 |
|
Pcie_Brige_Cfg.~(38).SchDoc.Zip
|
Test product V.01
|
2022-11-22 17:46:08 +08:00 |
|
Pcie_Brige_Cfg.~(39).SchDoc.Zip
|
Test product V.01
|
2022-11-22 17:46:08 +08:00 |
|
Pcie_Brige_Core.~(1).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(2).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(3).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(4).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(5).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(6).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(7).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(8).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(9).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(10).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(11).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(12).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(13).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(14).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(15).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(16).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(17).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(18).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(19).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(20).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(21).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(22).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(23).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(24).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(25).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(26).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Core.~(27).SchDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
Pcie_Brige_Core.~(28).SchDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
Pcie_Brige_Core.~(29).SchDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
Pcie_Brige_Core.~(30).SchDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
Pcie_Brige_Core.~(31).SchDoc.Zip
|
第一次布线完成
|
2022-11-21 13:17:30 +08:00 |
|
Pcie_Brige_Core.~(32).SchDoc.Zip
|
第一次布线完成
|
2022-11-21 13:17:30 +08:00 |
|
Pcie_Brige_Core.~(33).SchDoc.Zip
|
第一次布线完成
|
2022-11-21 13:17:30 +08:00 |
|
Pcie_Brige_Core.~(34).SchDoc.Zip
|
重新设置最小间距为6mil
|
2022-11-21 17:10:20 +08:00 |
|
Pcie_Brige_Core.~(35).SchDoc.Zip
|
Test product V.01
|
2022-11-22 17:46:08 +08:00 |
|
Pcie_Brige_Core.~(36).SchDoc.Zip
|
Test product V.01
|
2022-11-22 17:46:08 +08:00 |
|
Pcie_Brige_Core.~(37).SchDoc.Zip
|
Test product V.01
|
2022-11-22 17:46:08 +08:00 |
|
Pcie_Brige_Test.~(1).PrjPcb.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Test.~(2).PrjPcb.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_Test.~(3).PrjPcb.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
Pcie_Brige_Test.~(4).PrjPcb.Zip
|
Test product V.01
|
2022-11-22 17:46:08 +08:00 |
|
Pcie_Brige_Test.~(5).PrjPcb.Zip
|
Test product V.01
|
2022-11-22 17:46:08 +08:00 |
|
Pcie_Brige_pwr.~(1).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_pwr.~(2).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_pwr.~(3).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_pwr.~(4).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_pwr.~(5).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_pwr.~(6).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_pwr.~(7).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_pwr.~(8).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_pwr.~(9).SchDoc.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_Brige_pwr.~(10).SchDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
Pcie_Brige_pwr.~(11).SchDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
Pcie_Brige_pwr.~(12).SchDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
Pcie_Brige_pwr.~(13).SchDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
Pcie_Brige_pwr.~(14).SchDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
Pcie_Brige_pwr.~(15).SchDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
Pcie_Brige_pwr.~(16).SchDoc.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
Pcie_Brige_pwr.~(17).SchDoc.Zip
|
第一次布线完成
|
2022-11-21 13:17:30 +08:00 |
|
Pcie_Brige_pwr.~(18).SchDoc.Zip
|
重新设置最小间距为6mil
|
2022-11-21 17:10:20 +08:00 |
|
Pcie_Brige_pwr.~(19).SchDoc.Zip
|
重新设置最小间距为6mil
|
2022-11-21 17:10:20 +08:00 |
|
Pcie_Brige_pwr.~(20).SchDoc.Zip
|
重新设置最小间距为6mil
|
2022-11-21 17:10:20 +08:00 |
|
Pcie_Brige_pwr.~(21).SchDoc.Zip
|
重新设置最小间距为6mil
|
2022-11-21 17:10:20 +08:00 |
|
Pcie_Brige_pwr.~(22).SchDoc.Zip
|
重新设置最小间距为6mil
|
2022-11-21 17:10:20 +08:00 |
|
Pcie_Brige_pwr.~(23).SchDoc.Zip
|
重新设置最小间距为6mil
|
2022-11-21 17:10:20 +08:00 |
|
Pcie_Brige_pwr.~(24).SchDoc.Zip
|
Test product V.01
|
2022-11-22 17:46:08 +08:00 |
|
Pcie_Brige_pwr.~(25).SchDoc.Zip
|
Test product V.01
|
2022-11-22 17:46:08 +08:00 |
|
Pcie_Brige_pwr.~(26).SchDoc.Zip
|
Test product V.01
|
2022-11-22 17:46:08 +08:00 |
|
Pcie_PCB.~(1).PcbLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_PCB.~(2).PcbLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_PCB.~(3).PcbLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_PCB.~(4).PcbLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_PCB.~(5).PcbLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_PCB.~(6).PcbLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_PCB.~(7).PcbLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_PCB.~(8).PcbLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_PCB.~(9).PcbLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_PCB.~(10).PcbLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_PCB.~(11).PcbLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_PCB.~(12).PcbLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_PCB.~(13).PcbLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_PCB.~(14).PcbLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_PCB.~(15).PcbLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_PCB.~(16).PcbLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
Pcie_PCB.~(17).PcbLib.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
Pcie_PCB.~(18).PcbLib.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
Pcie_PCB.~(19).PcbLib.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
Pcie_PCB.~(20).PcbLib.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
Pcie_PCB.~(21).PcbLib.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
Pcie_PCB.~(22).PcbLib.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
Pcie_PCB.~(23).PcbLib.Zip
|
Test product V.01
|
2022-11-22 17:46:08 +08:00 |
|
Pcie_PCB.~(24).PcbLib.Zip
|
Test product V.01
|
2022-11-22 17:46:08 +08:00 |
|
pcie_test.~(1).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(2).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(3).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(4).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(5).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(6).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(7).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(8).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(9).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(10).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(11).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(12).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(13).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(14).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(15).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(16).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(17).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(18).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(19).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(20).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(21).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(22).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(23).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(24).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(25).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(26).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(27).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(28).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(29).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(30).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(31).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(32).SchLib.Zip
|
first commit
|
2022-11-20 21:10:53 +08:00 |
|
pcie_test.~(33).SchLib.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
pcie_test.~(34).SchLib.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
pcie_test.~(35).SchLib.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
pcie_test.~(36).SchLib.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
pcie_test.~(37).SchLib.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
pcie_test.~(38).SchLib.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
pcie_test.~(39).SchLib.Zip
|
PCB初始化
|
2022-11-21 00:10:13 +08:00 |
|
pcie_test.~(40).SchLib.Zip
|
Test product V.01
|
2022-11-22 17:46:08 +08:00 |
|
pcie_test.~(41).SchLib.Zip
|
Test product V.01
|
2022-11-22 17:46:08 +08:00 |
