Pcie_brige_test/Project Outputs for Pcie_Br.../Design Rule Check - PCIE_Br...

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</script><title>Design Rule Verification Report</title>
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<body onload=""><img ALT="Altium" src="
file://C:\Users\Public\Documents\Altium\AD22\Templates\AD_logo.png
"><h1>Design Rule Verification Report</h1>
<table class="header_holder">
<td class="column1">
<table class="front_matter">
<tr class="front_matter">
<td class="front_matter_column1">Date:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3">2022/11/21</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Time:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3">22:54:09</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Elapsed Time:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3">00:00:01</td>
</tr>
<tr class="front_matter">
<td class="front_matter_column1">Filename:</td>
<td class="front_matter_column2"></td>
<td class="front_matter_column3"><a href="file:///C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc" class="file"><acronym title="C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc">C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc</acronym></a></td>
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<td class="DRC_summary_header_col1">Warnings:</td>
<td class="DRC_summary_header_col2"></td>
<td class="DRC_summary_header_col3">0</td></tr>
<tr>
<td class="DRC_summary_header_col1">Rule Violations:</td>
<td class="DRC_summary_header_col2"></td>
<td class="DRC_summary_header_col3">0</td></tr>
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</table><a name="IDJYZLNTZZBM1NDROISYISOFLWRIQAHE5VKF2R33NK3RKWUTPZP3OF"><h2>Summary</h2></a><table>
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<th class="column1">Warnings</th>
<th class="column2">Count</th>
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<tr>
<td style="font-weight : bold; text-align : right" class="column1">Total</td>
<td style="font-weight : bold" class="column2">0</td>
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<th class="column1">Rule Violations</th>
<th class="column2">Count</th>
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<td class="column1"><a href="#IDAD0CDRRMUR3ZCE5RQLWZWFVO0MDEZVS5YWXQWLIQU12V2K2SACID">Clearance Constraint (Gap=6mil) (All),(All)</a></td>
<td class="column2">0</td>
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<td class="column1"><a href="#IDYQ0X0KORH4DEITHDZX5DMUDOTMNDP0M2QTVUECN4OET4L1GNR4VC">Short-Circuit Constraint (Allowed=No) (All),(All)</a></td>
<td class="column2">0</td>
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<td class="column1"><a href="#IDHJPAZM04KGL1KGYEZL0C2OJSENJZRVX5COC4BDHVOLJI2YO0SBMI">Un-Routed Net Constraint ( (All) )</a></td>
<td class="column2">0</td>
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<td class="column2">0</td>
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<td class="column1"><a href="#IDQRLAHWE2FS51HPTPGPWGRU0CFBKIY0S5U5ON5DPAONEVRVLSK0K">Width Constraint (Min=4mil) (Max=10mil) (Preferred=6mil) (All)</a></td>
<td class="column2">0</td>
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<td class="column1"><a href="#IDSOYQ2PZ2IDEX2WWS2OL2MLRXPMYS3NO0BQTV2BTYHZRBPS4533D">Routing Layers(All)</a></td>
<td class="column2">0</td>
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<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDYJMLYP2D3FFPSVAWBXLQIRDTIZXVSFKGP2OSVBVHGVNP2VQ1ZRF">Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=15.748mil) (PreferredHoleWidth=11.811mil) (MinWidth=11.811mil) (MaxWidth=23.622mil) (PreferedWidth=19.685mil) (All)</a></td>
<td class="column2">0</td>
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<td class="column1"><a href="#ID0FK5YGCEASBFEBEOJDJMQYY0HO2QDXSNPRMZKNHUXQWJ0XKTN3AL">Differential Pairs Uncoupled Length using the Gap Constraints (Min=4mil) (Max=10mil) (Prefered=6mil) and Width Constraints (Min=6mil) (Max=15mil) (Prefered=6mil) (All)</a></td>
<td class="column2">0</td>
</tr>
<tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
<td class="column1"><a href="#IDJEFXHB03YN3UGOPHMU5VA3WOFBZKPM34BRJCNEKGOPEJFSHKJQAH">Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)</a></td>
<td class="column2">0</td>
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<tr>
<td style="font-weight : bold; text-align : right" class="column1">Total</td>
<td style="font-weight : bold" class="column2">0</td>
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</table><br></body>
</html>