Design Rule Verification Report
Date:
2022/11/21
Time:
22:54:09
Elapsed Time:
00:00:01
Filename:
C:\Users\qp\Documents\Pcie_Brige_Test\PCIE_Brige_PCB.PcbDoc
Warnings:
0
Rule Violations:
0
Summary
Warnings
Count
Total
0
Rule Violations
Count
Clearance Constraint (Gap=6mil) (All),(All)
0
Short-Circuit Constraint (Allowed=No) (All),(All)
0
Un-Routed Net Constraint ( (All) )
0
Modified Polygon (Allow modified: No), (Allow shelved: No)
0
Width Constraint (Min=4mil) (Max=10mil) (Preferred=6mil) (All)
0
Routing Layers(All)
0
Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=15.748mil) (PreferredHoleWidth=11.811mil) (MinWidth=11.811mil) (MaxWidth=23.622mil) (PreferedWidth=19.685mil) (All)
0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=4mil) (Max=10mil) (Prefered=6mil) and Width Constraints (Min=6mil) (Max=15mil) (Prefered=6mil) (All)
0
Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
0
Total
0
