526 lines
14 KiB
C
526 lines
14 KiB
C
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-10-11 kyle first version
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*/
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#include <spi-bit-ops.h>
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#include <rtdevice.h>
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#define DBG_TAG "SPI"
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#ifdef RT_SPI_BITOPS_DEBUG
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#define DBG_LVL DBG_LOG
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#else
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#define DBG_LVL DBG_ERROR
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#endif
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#include <rtdbg.h>
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#define TOG_SCLK(ops) ops->tog_sclk(ops->data)
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#define SET_SCLK(ops, val) ops->set_sclk(ops->data, val)
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#define SET_MOSI(ops, val) ops->set_mosi(ops->data, val)
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#define SET_MISO(ops, val) ops->set_miso(ops->data, val)
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#define GET_SCLK(ops) ops->get_sclk(ops->data)
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#define GET_MOSI(ops) ops->get_mosi(ops->data)
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#define GET_MISO(ops) ops->get_miso(ops->data)
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#define DIR_MOSI(ops, val) ops->dir_mosi(ops->data, val)
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#define DIR_MISO(ops, val) ops->dir_miso(ops->data, val)
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rt_inline void spi_delay(struct rt_spi_bit_ops *ops)
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{
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ops->udelay((ops->delay_us + 1) >> 1);
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}
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rt_inline void spi_delay2(struct rt_spi_bit_ops *ops)
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{
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ops->udelay(ops->delay_us);
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}
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#define SCLK_H(ops) SET_SCLK(ops, 1)
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#define SCLK_L(ops) SET_SCLK(ops, 0)
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#define MOSI_H(ops) SET_MOSI(ops, 1)
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#define MOSI_L(ops) SET_MOSI(ops, 0)
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#define MOSI_IN(ops) DIR_MOSI(ops, 1)
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#define MOSI_OUT(ops) DIR_MOSI(ops, 0)
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#define MISO_IN(ops) DIR_MISO(ops, 1)
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#define MISO_OUT(ops) DIR_MISO(ops, 0)
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rt_inline rt_ssize_t spi_xfer_4line_data8(struct rt_spi_bit_ops *ops,
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struct rt_spi_configuration *config,
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const void *send_buf,
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void *recv_buf,
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rt_size_t length)
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{
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int i = 0;
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RT_ASSERT(ops != RT_NULL);
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RT_ASSERT(length != 0);
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{
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const rt_uint8_t *send_ptr = send_buf;
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rt_uint8_t *recv_ptr = recv_buf;
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rt_uint32_t size = length;
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while (size--)
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{
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rt_uint8_t tx_data = 0xFF;
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rt_uint8_t rx_data = 0xFF;
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rt_uint8_t bit = 0;
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if (send_buf != RT_NULL)
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{
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tx_data = *send_ptr++;
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}
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for (i = 0; i < 8; i++)
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{
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if (config->mode & RT_SPI_MSB) { bit = tx_data & (0x1 << (7 - i)); }
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else { bit = tx_data & (0x1 << i); }
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if (bit) MOSI_H(ops);
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else MOSI_L(ops);
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spi_delay2(ops);
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TOG_SCLK(ops);
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if (config->mode & RT_SPI_MSB) { rx_data <<= 1; bit = 0x01; }
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else { rx_data >>= 1; bit = 0x80; }
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if (GET_MISO(ops)) { rx_data |= bit; }
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else { rx_data &= ~bit; }
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spi_delay2(ops);
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if (!(config->mode & RT_SPI_CPHA) || (size != 0) || (i < 7))
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{
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TOG_SCLK(ops);
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}
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}
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if (recv_buf != RT_NULL)
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{
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*recv_ptr++ = rx_data;
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}
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}
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}
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return length;
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}
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rt_inline rt_ssize_t spi_xfer_4line_data16(struct rt_spi_bit_ops *ops,
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struct rt_spi_configuration *config,
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const void *send_buf,
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void *recv_buf,
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rt_size_t length)
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{
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int i = 0;
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RT_ASSERT(ops != RT_NULL);
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RT_ASSERT(length != 0);
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{
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const rt_uint16_t *send_ptr = send_buf;
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rt_uint16_t *recv_ptr = recv_buf;
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rt_uint32_t size = length;
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while (size--)
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{
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rt_uint16_t tx_data = 0xFFFF;
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rt_uint16_t rx_data = 0xFFFF;
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rt_uint16_t bit = 0;
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if (send_buf != RT_NULL)
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{
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tx_data = *send_ptr++;
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}
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for (i = 0; i < 16; i++)
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{
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if (config->mode & RT_SPI_MSB) { bit = tx_data & (0x1 << (15 - i)); }
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else { bit = tx_data & (0x1 << i); }
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if (bit) MOSI_H(ops);
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else MOSI_L(ops);
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spi_delay2(ops);
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TOG_SCLK(ops);
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if (config->mode & RT_SPI_MSB) { rx_data <<= 1; bit = 0x0001; }
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else { rx_data >>= 1; bit = 0x8000; }
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if (GET_MISO(ops)) { rx_data |= bit; }
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else { rx_data &= ~bit; }
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spi_delay2(ops);
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if (!(config->mode & RT_SPI_CPHA) || (size != 0) || (i < 15))
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{
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TOG_SCLK(ops);
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}
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}
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if (recv_buf != RT_NULL)
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{
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*recv_ptr++ = rx_data;
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}
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}
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}
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return length;
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}
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rt_inline rt_ssize_t spi_xfer_3line_data8(struct rt_spi_bit_ops *ops,
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struct rt_spi_configuration *config,
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const void *send_buf,
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void *recv_buf,
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rt_size_t length)
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{
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int i = 0;
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RT_ASSERT(ops != RT_NULL);
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RT_ASSERT(length != 0);
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{
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const rt_uint8_t *send_ptr = send_buf;
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rt_uint8_t *recv_ptr = recv_buf;
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rt_uint32_t size = length;
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rt_uint8_t send_flg = 0;
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if ((send_buf != RT_NULL) || (recv_buf == RT_NULL))
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{
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MOSI_OUT(ops);
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send_flg = 1;
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}
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else
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{
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MOSI_IN(ops);
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}
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while (size--)
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{
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rt_uint8_t tx_data = 0xFF;
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rt_uint8_t rx_data = 0xFF;
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rt_uint8_t bit = 0;
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if (send_buf != RT_NULL)
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{
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tx_data = *send_ptr++;
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}
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if (send_flg)
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{
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for (i = 0; i < 8; i++)
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{
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if (config->mode & RT_SPI_MSB) { bit = tx_data & (0x1 << (7 - i)); }
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else { bit = tx_data & (0x1 << i); }
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if (bit) MOSI_H(ops);
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else MOSI_L(ops);
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spi_delay2(ops);
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TOG_SCLK(ops);
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spi_delay2(ops);
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if (!(config->mode & RT_SPI_CPHA) || (size != 0) || (i < 7))
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{
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TOG_SCLK(ops);
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}
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}
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rx_data = tx_data;
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}
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else
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{
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for (i = 0; i < 8; i++)
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{
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spi_delay2(ops);
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TOG_SCLK(ops);
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if (config->mode & RT_SPI_MSB) { rx_data <<= 1; bit = 0x01; }
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else { rx_data >>= 1; bit = 0x80; }
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if (GET_MOSI(ops)) { rx_data |= bit; }
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else { rx_data &= ~bit; }
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spi_delay2(ops);
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if (!(config->mode & RT_SPI_CPHA) || (size != 0) || (i < 7))
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{
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TOG_SCLK(ops);
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}
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}
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}
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if (recv_buf != RT_NULL)
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{
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*recv_ptr++ = rx_data;
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}
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}
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if (!send_flg)
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{
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MOSI_OUT(ops);
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}
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}
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return length;
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}
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rt_inline rt_ssize_t spi_xfer_3line_data16(struct rt_spi_bit_ops *ops,
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struct rt_spi_configuration *config,
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const void *send_buf,
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void *recv_buf,
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rt_size_t length)
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{
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int i = 0;
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RT_ASSERT(ops != RT_NULL);
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RT_ASSERT(length != 0);
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{
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const rt_uint16_t *send_ptr = send_buf;
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rt_uint16_t *recv_ptr = recv_buf;
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rt_uint32_t size = length;
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rt_uint8_t send_flg = 0;
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if ((send_buf != RT_NULL) || (recv_buf == RT_NULL))
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{
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MOSI_OUT(ops);
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send_flg = 1;
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}
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else
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{
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MOSI_IN(ops);
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}
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while (size--)
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{
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rt_uint16_t tx_data = 0xFFFF;
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rt_uint16_t rx_data = 0xFFFF;
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rt_uint16_t bit = 0;
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if (send_buf != RT_NULL)
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{
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tx_data = *send_ptr++;
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}
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if (send_flg)
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{
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for (i = 0; i < 16; i++)
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{
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if (config->mode & RT_SPI_MSB) { bit = tx_data & (0x1 << (15 - i)); }
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else { bit = tx_data & (0x1 << i); }
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if (bit) MOSI_H(ops);
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else MOSI_L(ops);
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spi_delay2(ops);
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TOG_SCLK(ops);
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spi_delay2(ops);
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if (!(config->mode & RT_SPI_CPHA) || (size != 0) || (i < 15))
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{
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TOG_SCLK(ops);
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}
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}
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rx_data = tx_data;
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}
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else
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{
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for (i = 0; i < 16; i++)
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{
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spi_delay2(ops);
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TOG_SCLK(ops);
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if (config->mode & RT_SPI_MSB) { rx_data <<= 1; bit = 0x0001; }
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else { rx_data >>= 1; bit = 0x8000; }
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if (GET_MOSI(ops)) { rx_data |= bit; }
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else { rx_data &= ~bit; }
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spi_delay2(ops);
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if (!(config->mode & RT_SPI_CPHA) || (size != 0) || (i < 15))
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{
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TOG_SCLK(ops);
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}
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}
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}
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if (recv_buf != RT_NULL)
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{
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*recv_ptr++ = rx_data;
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}
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}
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if (!send_flg)
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{
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MOSI_OUT(ops);
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}
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}
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return length;
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}
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rt_err_t spi_bit_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration)
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{
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struct rt_spi_bit_obj *obj = rt_container_of(device->bus, struct rt_spi_bit_obj, bus);
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struct rt_spi_bit_ops *ops = obj->ops;
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(configuration != RT_NULL);
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if (configuration->mode & RT_SPI_SLAVE)
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{
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return -RT_EIO;
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}
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if (configuration->mode & RT_SPI_CPOL)
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{
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SCLK_H(ops);
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}
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else
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{
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SCLK_L(ops);
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|
}
|
||
|
|
|
||
|
|
if (configuration->max_hz < 200000)
|
||
|
|
{
|
||
|
|
ops->delay_us = 1;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
ops->delay_us = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
rt_memcpy(&obj->config, configuration, sizeof(struct rt_spi_configuration));
|
||
|
|
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
rt_ssize_t spi_bit_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
|
||
|
|
{
|
||
|
|
struct rt_spi_bit_obj *obj = rt_container_of(device->bus, struct rt_spi_bit_obj, bus);
|
||
|
|
struct rt_spi_bit_ops *ops = obj->ops;
|
||
|
|
struct rt_spi_configuration *config = &obj->config;
|
||
|
|
rt_base_t cs_pin = device->cs_pin;
|
||
|
|
|
||
|
|
RT_ASSERT(device != NULL);
|
||
|
|
RT_ASSERT(message != NULL);
|
||
|
|
|
||
|
|
#ifdef RT_SPI_BITOPS_DEBUG
|
||
|
|
if (!ops->tog_sclk || !ops->set_sclk || !ops->get_sclk)
|
||
|
|
{
|
||
|
|
LOG_E("SPI bus error, SCLK line not defined");
|
||
|
|
}
|
||
|
|
if (!ops->set_mosi || !ops->get_mosi)
|
||
|
|
{
|
||
|
|
LOG_E("SPI bus error, MOSI line not defined");
|
||
|
|
}
|
||
|
|
if (!ops->set_miso || !ops->get_miso)
|
||
|
|
{
|
||
|
|
LOG_E("SPI bus error, MISO line not defined");
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* take CS */
|
||
|
|
if (message->cs_take && (cs_pin != PIN_NONE))
|
||
|
|
{
|
||
|
|
LOG_I("spi take cs\n");
|
||
|
|
rt_pin_write(cs_pin, PIN_LOW);
|
||
|
|
spi_delay(ops);
|
||
|
|
|
||
|
|
/* spi phase */
|
||
|
|
if (config->mode & RT_SPI_CPHA)
|
||
|
|
{
|
||
|
|
spi_delay(ops);
|
||
|
|
TOG_SCLK(ops);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (config->mode & RT_SPI_3WIRE)
|
||
|
|
{
|
||
|
|
if (config->data_width <= 8)
|
||
|
|
{
|
||
|
|
spi_xfer_3line_data8(ops,
|
||
|
|
config,
|
||
|
|
message->send_buf,
|
||
|
|
message->recv_buf,
|
||
|
|
message->length);
|
||
|
|
}
|
||
|
|
else if (config->data_width <= 16)
|
||
|
|
{
|
||
|
|
spi_xfer_3line_data16(ops,
|
||
|
|
config,
|
||
|
|
message->send_buf,
|
||
|
|
message->recv_buf,
|
||
|
|
message->length);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
if (config->data_width <= 8)
|
||
|
|
{
|
||
|
|
spi_xfer_4line_data8(ops,
|
||
|
|
config,
|
||
|
|
message->send_buf,
|
||
|
|
message->recv_buf,
|
||
|
|
message->length);
|
||
|
|
}
|
||
|
|
else if (config->data_width <= 16)
|
||
|
|
{
|
||
|
|
spi_xfer_4line_data16(ops,
|
||
|
|
config,
|
||
|
|
message->send_buf,
|
||
|
|
message->recv_buf,
|
||
|
|
message->length);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* release CS */
|
||
|
|
if (message->cs_release && (cs_pin != PIN_NONE))
|
||
|
|
{
|
||
|
|
spi_delay(ops);
|
||
|
|
rt_pin_write(cs_pin, PIN_HIGH);
|
||
|
|
LOG_I("spi release cs\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
return message->length;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct rt_spi_ops spi_bit_bus_ops =
|
||
|
|
{
|
||
|
|
.configure = spi_bit_configure,
|
||
|
|
.xfer = spi_bit_xfer,
|
||
|
|
};
|
||
|
|
|
||
|
|
rt_err_t rt_spi_bit_add_bus(struct rt_spi_bit_obj *obj,
|
||
|
|
const char *bus_name,
|
||
|
|
struct rt_spi_bit_ops *ops)
|
||
|
|
{
|
||
|
|
obj->ops = ops;
|
||
|
|
obj->config.data_width = 8;
|
||
|
|
obj->config.max_hz = 1 * 1000 * 1000;
|
||
|
|
obj->config.mode = RT_SPI_MASTER | RT_SPI_MSB | RT_SPI_MODE_0;
|
||
|
|
|
||
|
|
/* idle status */
|
||
|
|
if (obj->config.mode & RT_SPI_CPOL) SCLK_H(ops);
|
||
|
|
else SCLK_L(ops);
|
||
|
|
|
||
|
|
return rt_spi_bus_register(&obj->bus, bus_name, &spi_bit_bus_ops);
|
||
|
|
}
|