505 lines
14 KiB
ArmAsm
505 lines
14 KiB
ArmAsm
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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*/
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@-------------------------------------------------------------------------------
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@ sys_core.asm
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@
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@ (c) Texas Instruments 2009-2013, All rights reserved.
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@
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#include <rtconfig.h>
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.equ Mode_USR, 0x10
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.equ Mode_FIQ, 0x11
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.equ Mode_IRQ, 0x12
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.equ Mode_SVC, 0x13
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.equ Mode_ABT, 0x17
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.equ Mode_UND, 0x1B
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.equ Mode_SYS, 0x1F
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.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled
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.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled
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.equ UND_Stack_Size, 0x00000000
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.equ SVC_Stack_Size, 0x00000000
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.equ ABT_Stack_Size, 0x00000000
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.equ FIQ_Stack_Size, 0x00001000
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.equ IRQ_Stack_Size, 0x00001000
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.section .bss.noinit
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/* stack */
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.globl stack_start
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.globl stack_top
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.align 3
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stack_start:
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.rept (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size)
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.byte 0
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.endr
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stack_top:
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.section .text, "ax"
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.text
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.arm
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.globl _c_int00
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.globl _reset
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_reset:
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@-------------------------------------------------------------------------------
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@ Initialize CPU Registers
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@ After reset, the CPU is in the Supervisor mode (M = 10011)
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mov r0, #0x0000
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mov r1, #0x0000
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mov r2, #0x0000
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mov r3, #0x0000
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mov r4, #0x0000
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mov r5, #0x0000
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mov r6, #0x0000
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mov r7, #0x0000
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mov r8, #0x0000
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mov r9, #0x0000
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mov r10, #0x0000
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mov r11, #0x0000
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mov r12, #0x0000
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mov r13, #0x0000
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mrs r1, cpsr
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msr spsr_cxsf, r1
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cpsid if, #19
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#if defined (__VFP_FP__) && !defined(__SOFTFP__) && defined(RT_VFP_LAZY_STACKING)
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@ Turn on FPV coprocessor
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mrc p15, #0x00, r2, c1, c0, #0x02
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orr r2, r2, #0xF00000
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mcr p15, #0x00, r2, c1, c0, #0x02
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fmrx r2, fpexc
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orr r2, r2, #0x40000000
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fmxr fpexc, r2
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#endif
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@-------------------------------------------------------------------------------
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@ Initialize Stack Pointers
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ldr r0, =stack_top
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@ Set the startup stack for svc
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mov sp, r0
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@ Enter Undefined Instruction Mode and set its Stack Pointer
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msr cpsr_c, #Mode_UND|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #UND_Stack_Size
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@ Enter Abort Mode and set its Stack Pointer
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msr cpsr_c, #Mode_ABT|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #ABT_Stack_Size
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@ Enter FIQ Mode and set its Stack Pointer
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msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #FIQ_Stack_Size
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@ Enter IRQ Mode and set its Stack Pointer
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msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #IRQ_Stack_Size
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@ Switch back to SVC
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msr cpsr_c, #Mode_SVC|I_Bit|F_Bit
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bl next1
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next1:
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bl next2
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next2:
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bl next3
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next3:
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bl next4
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next4:
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ldr lr, =_c_int00
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bx lr
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.globl data_init
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data_init:
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/* copy .data to SRAM */
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ldr r1, =_sidata /* .data start in image */
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ldr r2, =_edata /* .data end in image */
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ldr r3, =_sdata /* sram data start */
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data_loop:
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ldr r0, [r1, #0]
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str r0, [r3]
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add r1, r1, #4
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add r3, r3, #4
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cmp r3, r2 /* check if data to clear */
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blo data_loop /* loop until done */
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/* clear .bss */
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mov r0,#0 /* get a zero */
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ldr r1,=__bss_start /* bss start */
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ldr r2,=__bss_end /* bss end */
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bss_loop:
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cmp r1,r2 /* check if data to clear */
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strlo r0,[r1],#4 /* clear 4 bytes */
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blo bss_loop /* loop until done */
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/* call C++ constructors of global objects */
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ldr r0, =__ctors_start__
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ldr r1, =__ctors_end__
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ctor_loop:
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cmp r0, r1
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beq ctor_end
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ldr r2, [r0], #4
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stmfd sp!, {r0-r3, ip, lr}
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mov lr, pc
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bx r2
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ldmfd sp!, {r0-r3, ip, lr}
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b ctor_loop
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ctor_end:
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bx lr
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@-------------------------------------------------------------------------------
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@ Enable RAM ECC Support
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.globl _coreEnableRamEcc_
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_coreEnableRamEcc_:
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stmfd sp!, {r0}
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mrc p15, #0x00, r0, c1, c0, #0x01
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orr r0, r0, #0x0C000000
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mcr p15, #0x00, r0, c1, c0, #0x01
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ldmfd sp!, {r0}
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bx lr
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@-------------------------------------------------------------------------------
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@ Disable RAM ECC Support
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.globl _coreDisableRamEcc_
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_coreDisableRamEcc_:
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stmfd sp!, {r0}
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mrc p15, #0x00, r0, c1, c0, #0x01
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bic r0, r0, #0x0C000000
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mcr p15, #0x00, r0, c1, c0, #0x01
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ldmfd sp!, {r0}
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bx lr
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@-------------------------------------------------------------------------------
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@ Enable Flash ECC Support
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.globl _coreEnableFlashEcc_
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_coreEnableFlashEcc_:
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stmfd sp!, {r0}
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mrc p15, #0x00, r0, c1, c0, #0x01
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orr r0, r0, #0x02000000
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dmb
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mcr p15, #0x00, r0, c1, c0, #0x01
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ldmfd sp!, {r0}
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bx lr
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@-------------------------------------------------------------------------------
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@ Disable Flash ECC Support
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.globl _coreDisableFlashEcc_
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_coreDisableFlashEcc_:
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stmfd sp!, {r0}
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mrc p15, #0x00, r0, c1, c0, #0x01
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bic r0, r0, #0x02000000
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mcr p15, #0x00, r0, c1, c0, #0x01
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ldmfd sp!, {r0}
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bx lr
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@-------------------------------------------------------------------------------
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@ Get data fault status register
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.globl _coreGetDataFault_
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_coreGetDataFault_:
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mrc p15, #0, r0, c5, c0, #0
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bx lr
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@-------------------------------------------------------------------------------
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@ Clear data fault status register
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.globl _coreClearDataFault_
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_coreClearDataFault_:
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stmfd sp!, {r0}
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mov r0, #0
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mcr p15, #0, r0, c5, c0, #0
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ldmfd sp!, {r0}
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bx lr
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@-------------------------------------------------------------------------------
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@ Get instruction fault status register
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.globl _coreGetInstructionFault_
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_coreGetInstructionFault_:
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mrc p15, #0, r0, c5, c0, #1
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bx lr
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@-------------------------------------------------------------------------------
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@ Clear instruction fault status register
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.globl _coreClearInstructionFault_
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_coreClearInstructionFault_:
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stmfd sp!, {r0}
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mov r0, #0
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mcr p15, #0, r0, c5, c0, #1
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ldmfd sp!, {r0}
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bx lr
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@-------------------------------------------------------------------------------
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@ Get data fault address register
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.globl _coreGetDataFaultAddress_
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_coreGetDataFaultAddress_:
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mrc p15, #0, r0, c6, c0, #0
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bx lr
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@-------------------------------------------------------------------------------
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@ Clear data fault address register
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.globl _coreClearDataFaultAddress_
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_coreClearDataFaultAddress_:
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stmfd sp!, {r0}
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mov r0, #0
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mcr p15, #0, r0, c6, c0, #0
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ldmfd sp!, {r0}
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bx lr
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@-------------------------------------------------------------------------------
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@ Get instruction fault address register
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.globl _coreGetInstructionFaultAddress_
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_coreGetInstructionFaultAddress_:
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mrc p15, #0, r0, c6, c0, #2
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bx lr
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@-------------------------------------------------------------------------------
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@ Clear instruction fault address register
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.globl _coreClearInstructionFaultAddress_
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_coreClearInstructionFaultAddress_:
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stmfd sp!, {r0}
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mov r0, #0
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mcr p15, #0, r0, c6, c0, #2
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ldmfd sp!, {r0}
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bx lr
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@-------------------------------------------------------------------------------
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@ Get auxiliary data fault status register
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.globl _coreGetAuxiliaryDataFault_
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_coreGetAuxiliaryDataFault_:
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mrc p15, #0, r0, c5, c1, #0
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bx lr
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@-------------------------------------------------------------------------------
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@ Clear auxiliary data fault status register
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.globl _coreClearAuxiliaryDataFault_
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_coreClearAuxiliaryDataFault_:
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stmfd sp!, {r0}
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mov r0, #0
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mcr p15, #0, r0, c5, c1, #0
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ldmfd sp!, {r0}
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bx lr
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@-------------------------------------------------------------------------------
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@ Get auxiliary instruction fault status register
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.globl _coreGetAuxiliaryInstructionFault_
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_coreGetAuxiliaryInstructionFault_:
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mrc p15, #0, r0, c5, c1, #1
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bx lr
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@-------------------------------------------------------------------------------
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@ Clear auxiliary instruction fault status register
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.globl _coreClearAuxiliaryInstructionFault_
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_coreClearAuxiliaryInstructionFault_:
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stmfd sp!, {r0}
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mov r0, #0
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mrc p15, #0, r0, c5, c1, #1
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ldmfd sp!, {r0}
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bx lr
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@-------------------------------------------------------------------------------
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@ Clear ESM CCM errorss
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.globl _esmCcmErrorsClear_
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_esmCcmErrorsClear_:
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stmfd sp!, {r0-r2}
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ldr r0, ESMSR1_REG @ load the ESMSR1 status register address
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ldr r2, ESMSR1_ERR_CLR
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str r2, [r0] @ clear the ESMSR1 register
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ldr r0, ESMSR2_REG @ load the ESMSR2 status register address
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ldr r2, ESMSR2_ERR_CLR
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str r2, [r0] @ clear the ESMSR2 register
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ldr r0, ESMSSR2_REG @ load the ESMSSR2 status register address
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ldr r2, ESMSSR2_ERR_CLR
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str r2, [r0] @ clear the ESMSSR2 register
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ldr r0, ESMKEY_REG @ load the ESMKEY register address
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mov r2, #0x5 @ load R2 with 0x5
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str r2, [r0] @ clear the ESMKEY register
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ldr r0, VIM_INTREQ @ load the INTREQ register address
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ldr r2, VIM_INT_CLR
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str r2, [r0] @ clear the INTREQ register
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ldr r0, CCMR4_STAT_REG @ load the CCMR4 status register address
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ldr r2, CCMR4_ERR_CLR
|
||
|
|
str r2, [r0] @ clear the CCMR4 status register
|
||
|
|
ldmfd sp!, {r0-r2}
|
||
|
|
bx lr
|
||
|
|
|
||
|
|
ESMSR1_REG: .word 0xFFFFF518
|
||
|
|
ESMSR2_REG: .word 0xFFFFF51C
|
||
|
|
ESMSR3_REG: .word 0xFFFFF520
|
||
|
|
ESMKEY_REG: .word 0xFFFFF538
|
||
|
|
ESMSSR2_REG: .word 0xFFFFF53C
|
||
|
|
CCMR4_STAT_REG: .word 0xFFFFF600
|
||
|
|
ERR_CLR_WRD: .word 0xFFFFFFFF
|
||
|
|
CCMR4_ERR_CLR: .word 0x00010000
|
||
|
|
ESMSR1_ERR_CLR: .word 0x80000000
|
||
|
|
ESMSR2_ERR_CLR: .word 0x00000004
|
||
|
|
ESMSSR2_ERR_CLR: .word 0x00000004
|
||
|
|
VIM_INT_CLR: .word 0x00000001
|
||
|
|
VIM_INTREQ: .word 0xFFFFFE20
|
||
|
|
|
||
|
|
|
||
|
|
@-------------------------------------------------------------------------------
|
||
|
|
@ Work Around for Errata CORTEX-R4#57:
|
||
|
|
@
|
||
|
|
@ Errata Description:
|
||
|
|
@ Conditional VMRS APSR_Nzcv, FPSCR May Evaluate With Incorrect Flags
|
||
|
|
@ Workaround:
|
||
|
|
@ Disable out-of-order single-precision floating point
|
||
|
|
@ multiply-accumulate instruction completion
|
||
|
|
|
||
|
|
.globl _errata_CORTEXR4_57_
|
||
|
|
_errata_CORTEXR4_57_:
|
||
|
|
|
||
|
|
push {r0}
|
||
|
|
mrc p15, #0, r0, c15, c0, #0 @ Read Secondary Auxiliary Control Register
|
||
|
|
orr r0, r0, #0x10000 @ Set BIT 16 (Set DOOFMACS)
|
||
|
|
mcr p15, #0, r0, c15, c0, #0 @ Write Secondary Auxiliary Control Register
|
||
|
|
pop {r0}
|
||
|
|
bx lr
|
||
|
|
|
||
|
|
@-------------------------------------------------------------------------------
|
||
|
|
@ Work Around for Errata CORTEX-R4#66:
|
||
|
|
@
|
||
|
|
@ Errata Description:
|
||
|
|
@ Register Corruption During A Load-Multiple Instruction At
|
||
|
|
@ an Exception Vector
|
||
|
|
@ Workaround:
|
||
|
|
@ Disable out-of-order completion for divide instructions in
|
||
|
|
@ Auxiliary Control register
|
||
|
|
|
||
|
|
.globl _errata_CORTEXR4_66_
|
||
|
|
_errata_CORTEXR4_66_:
|
||
|
|
|
||
|
|
push {r0}
|
||
|
|
mrc p15, #0, r0, c1, c0, #1 @ Read Auxiliary Control register
|
||
|
|
orr r0, r0, #0x80 @ Set BIT 7 (Disable out-of-order completion
|
||
|
|
@ for divide instructions.)
|
||
|
|
mcr p15, #0, r0, c1, c0, #1 @ Write Auxiliary Control register
|
||
|
|
pop {r0}
|
||
|
|
bx lr
|
||
|
|
|
||
|
|
.globl turnon_VFP
|
||
|
|
turnon_VFP:
|
||
|
|
@ Enable FPV
|
||
|
|
STMDB sp!, {r0}
|
||
|
|
fmrx r0, fpexc
|
||
|
|
orr r0, r0, #0x40000000
|
||
|
|
fmxr fpexc, r0
|
||
|
|
LDMIA sp!, {r0}
|
||
|
|
subs pc, lr, #4
|
||
|
|
|
||
|
|
.macro push_svc_reg
|
||
|
|
sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */
|
||
|
|
stmia sp, {r0 - r12} @/* Calling r0-r12 */
|
||
|
|
mov r0, sp
|
||
|
|
mrs r6, spsr @/* Save CPSR */
|
||
|
|
str lr, [r0, #15*4] @/* Push PC */
|
||
|
|
str r6, [r0, #16*4] @/* Push CPSR */
|
||
|
|
cps #Mode_SVC
|
||
|
|
str sp, [r0, #13*4] @/* Save calling SP */
|
||
|
|
str lr, [r0, #14*4] @/* Save calling PC */
|
||
|
|
.endm
|
||
|
|
|
||
|
|
.globl vector_svc
|
||
|
|
vector_svc:
|
||
|
|
push_svc_reg
|
||
|
|
bl rt_hw_trap_svc
|
||
|
|
b .
|
||
|
|
|
||
|
|
.globl vector_pabort
|
||
|
|
vector_pabort:
|
||
|
|
push_svc_reg
|
||
|
|
bl rt_hw_trap_pabt
|
||
|
|
b .
|
||
|
|
|
||
|
|
.globl vector_dabort
|
||
|
|
vector_dabort:
|
||
|
|
push_svc_reg
|
||
|
|
bl rt_hw_trap_dabt
|
||
|
|
b .
|
||
|
|
|
||
|
|
.globl vector_resv
|
||
|
|
vector_resv:
|
||
|
|
push_svc_reg
|
||
|
|
bl rt_hw_trap_resv
|
||
|
|
b .
|