254 lines
6.0 KiB
ArmAsm
254 lines
6.0 KiB
ArmAsm
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2006-09-06 XuXinming first version
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* 2006-09-20 Bernard clean the code
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*/
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/**
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* @addtogroup S3C44B0
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*/
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/*@{*/
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.section .init, "ax"
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.code 32
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.globl _start
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_start:
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b reset
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ldr pc, _vector_undef
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ldr pc, _vector_swi
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ldr pc, _vector_pabt
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ldr pc, _vector_dabt
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ldr pc, _vector_resv
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ldr pc, _vector_irq
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ldr pc, _vector_fiq
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_vector_undef: .word vector_undef
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_vector_swi: .word vector_swi
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_vector_pabt: .word vector_pabt
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_vector_dabt: .word vector_dabt
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_vector_resv: .word vector_resv
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_vector_irq: .word vector_irq
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_vector_fiq: .word vector_fiq
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.text
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.code 32
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/*
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* rtthread kernel start and end
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* which are defined in linker script
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*/
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.globl _rtthread_start
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_rtthread_start:.word _start
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.globl _rtthread_end
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_rtthread_end: .word _end
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/*
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* rtthread bss start and end
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* which are defined in linker script
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*/
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.globl _bss_start
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_bss_start: .word __bss_start
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.globl _bss_end
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_bss_end: .word __bss_end
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#if defined(__FLASH_BUILD__)
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/*
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* TEXT_BASE,
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* which is defined in macro of make
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*/
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_TEXT_BASE: .word TEXT_BASE
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#endif
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.equ WTCON, 0x1d30000
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.equ INTCON, 0x1e00000
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.equ INTMSK, 0x1e0000c
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/* the system entry */
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reset:
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/* enter svc mode */
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msr cpsr_c, #SVCMODE|NOINT
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/*watch dog disable */
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ldr r0,=WTCON
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ldr r1,=0x0
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str r1,[r0]
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/* all interrupt disable */
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ldr r0,=INTMSK
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ldr r1,=0x07ffffff
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str r1,[r0]
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ldr r1, =INTCON
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ldr r0, =0x05
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str r0, [r1]
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#if defined(__FLASH_BUILD__)
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/* init lowlevel */
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bl lowlevel_init
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#endif
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/* setup stack */
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bl stack_setup
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#if defined(__FLASH_BUILD__)
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mov r0, #0x0 /* r0 <- flash base address */
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ldr r1, _TEXT_BASE /* r1 <- the taget address */
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ldr r2, _rtthread_start
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ldr r3, _bss_start
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sub r2, r3, r2 /* r2 <- size of rtthread kernel */
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add r2, r0, r2 /* r2 <- source end address */
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copy_loop:
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ldmia r0!, {r3-r10} /* copy from source address [r0] */
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stmia r1!, {r3-r10} /* copy to target address [r1] */
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cmp r0, r2 /* until source end address [r2] */
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ble copy_loop
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#endif
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/* start RT-Thread Kernel */
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ldr pc, _rtthread_startup
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_rtthread_startup: .word rtthread_startup
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.equ USERMODE, 0x10
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.equ FIQMODE, 0x11
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.equ IRQMODE, 0x12
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.equ SVCMODE, 0x13
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.equ ABORTMODE, 0x17
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.equ UNDEFMODE, 0x1b
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.equ MODEMASK, 0x1f
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.equ NOINT, 0xc0
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/* exception handlers */
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vector_undef: bl rt_hw_trap_udef
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vector_swi: bl rt_hw_trap_swi
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vector_pabt: bl rt_hw_trap_pabt
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vector_dabt: bl rt_hw_trap_dabt
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vector_resv: bl rt_hw_trap_resv
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.globl rt_interrupt_enter
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.globl rt_interrupt_leave
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.globl rt_thread_switch_interrupt_flag
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.globl rt_interrupt_from_thread
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.globl rt_interrupt_to_thread
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vector_irq:
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stmfd sp!, {r0-r12,lr}
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bl led_off
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bl rt_interrupt_enter
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bl rt_hw_trap_irq
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bl rt_interrupt_leave
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/* if rt_thread_switch_interrupt_flag set, jump to _interrupt_thread_switch and don't return */
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ldr r0, =rt_thread_switch_interrupt_flag
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ldr r1, [r0]
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cmp r1, #1
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beq _interrupt_thread_switch
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ldmfd sp!, {r0-r12,lr}
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subs pc, lr, #4
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.align 5
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vector_fiq:
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stmfd sp!,{r0-r7,lr}
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bl rt_hw_trap_fiq
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ldmfd sp!,{r0-r7,lr}
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subs pc,lr,#4
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_interrupt_thread_switch:
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mov r1, #0 @ clear rt_thread_switch_interrupt_flag
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str r1, [r0]
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ldmfd sp!, {r0-r12,lr} @ reload saved registers
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stmfd sp!, {r0-r3} @ save r0-r3
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mov r1, sp
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add sp, sp, #16 @ restore sp
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sub r2, lr, #4 @ save old task's pc to r2
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mrs r3, spsr @ disable interrupt
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orr r0, r3, #NOINT
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msr spsr_c, r0
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ldr r0, =.+8 @ switch to interrupted task's stack
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movs pc, r0
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stmfd sp!, {r2} @ push old task's pc
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stmfd sp!, {r4-r12,lr} @ push old task's lr,r12-r4
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mov r4, r1 @ Special optimised code below
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mov r5, r3
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ldmfd r4!, {r0-r3}
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stmfd sp!, {r0-r3} @ push old task's r3-r0
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stmfd sp!, {r5} @ push old task's psr
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mrs r4, spsr
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stmfd sp!, {r4} @ push old task's spsr
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ldr r4, =rt_interrupt_from_thread
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ldr r5, [r4]
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str sp, [r5] @ store sp in preempted tasks's TCB
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ldr r6, =rt_interrupt_to_thread
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ldr r6, [r6]
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ldr sp, [r6] @ get new task's stack pointer
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ldmfd sp!, {r4} @ pop new task's spsr
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msr SPSR_cxsf, r4
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ldmfd sp!, {r4} @ pop new task's psr
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msr CPSR_cxsf, r4
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ldmfd sp!, {r0-r12,lr,pc} @ pop new task's r0-r12,lr & pc
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/* each mode stack memory */
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UNDSTACK_START: .word _undefined_stack_start + 128
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ABTSTACK_START: .word _abort_stack_start + 128
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FIQSTACK_START: .word _fiq_stack_start + 1024
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IRQSTACK_START: .word _irq_stack_start + 1024
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SVCSTACK_START: .word _svc_stack_start + 4096
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stack_setup:
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/* undefined instruction mode */
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msr cpsr_c, #UNDEFMODE|NOINT
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ldr sp, UNDSTACK_START
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/* abort mode */
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msr cpsr_c, #ABORTMODE|NOINT
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ldr sp, ABTSTACK_START
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/* FIQ mode */
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msr cpsr_c, #FIQMODE|NOINT
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ldr sp, FIQSTACK_START
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/* IRQ mode */
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msr cpsr_c, #IRQMODE|NOINT
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ldr sp, IRQSTACK_START
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/* supervisor mode */
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msr cpsr_c, #SVCMODE|NOINT
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ldr sp, SVCSTACK_START
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mov pc,lr @ The LR register may be not valid for the mode changes.
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.globl led_on
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led_on:
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ldr r1, =0x1d20014 @ r1<-PDATC
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ldr r0, [r1] @ r0<-[r1]
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orr r0, r0, #0x0e @ r0=r0 or 0x0e
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str r0, [r1] @ r0->[r1]
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mov pc, lr
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.globl led_off
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led_off:
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ldr r1, =0x1d20010 @ r1<-PCONC
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ldr r0, =0x5f555555 @ r0<-0x5f555555
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str r0, [r1] @ r0->[r1]
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ldr r1, =0x1d20014 @ r1<-PDATC
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ldr r0, =0x0 @ r0<-00
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str r0, [r1] @ r0->[r1]
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mov pc, lr
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