256 lines
8.4 KiB
C
256 lines
8.4 KiB
C
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2013-07-06 Bernard first version
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*/
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#ifndef __INTERRUPT_H__
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#define __INTERRUPT_H__
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#define INT_IRQ 0x00
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#define INT_FIQ 0x01
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/*************************************************************************\
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* Registers Definition
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\*************************************************************************/
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#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0)
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#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10)
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#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14)
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#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40)
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#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44)
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#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48)
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#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c)
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#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50)
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#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60)
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#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64)
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#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68)
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#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c)
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#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04))
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#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20))
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#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20))
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#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20))
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#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20))
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#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20))
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#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20))
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#define INTC_PENDING_IRQ(hw_base, n) REG32((hw_base) + 0x98 + ((n) * 0x20))
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#define INTC_PENDING_FIQ(hw_base, n) REG32((hw_base) + 0x9c + ((n) * 0x20))
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#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04))
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/**************************************************************************\
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* Field Definition Macros
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\**************************************************************************/
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/* REVISION */
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#define INTC_REVISION_REV (0x000000FFu)
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#define INTC_REVISION_REV_SHIFT (0x00000000u)
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/* SYSCONFIG */
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#define INTC_SYSCONFIG_SOFTRESET (0x00000002u)
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#define INTC_SYSCONFIG_SOFTRESET_SHIFT (0x00000001u)
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#define INTC_SYSCONFIG_AUTOIDLE (0x00000001u)
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#define INTC_SYSCONFIG_AUTOIDLE_SHIFT (0x00000000u)
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/* SYSSTATUS */
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#define INTC_SYSSTATUS_RESETDONE (0x00000001u)
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#define INTC_SYSSTATUS_RESETDONE_SHIFT (0x00000000u)
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/* SIR_IRQ */
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#define INTC_SIR_IRQ_SPURIOUSIRQ (0xFFFFFF80u)
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#define INTC_SIR_IRQ_SPURIOUSIRQ_SHIFT (0x00000007u)
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#define INTC_SIR_IRQ_ACTIVEIRQ (0x0000007F)
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#define INTC_SIR_IRQ_ACTIVEIRQ_SHIFT (0x00000000)
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/* SIR_FIQ */
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#define INTC_SIR_FIQ_SPURIOUSFIQ (0xFFFFFF80)
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#define INTC_SIR_FIQ_SPURIOUSFIQ_SHIFT (0x00000007)
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#define INTC_SIR_FIQ_ACTIVEFIQ (0x0000007F)
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#define INTC_SIR_FIQ_ACTIVEFIQ_SHIFT (0x00000000)
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/* CONTROL */
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#define INTC_CONTROL_NEWFIQAGR (0x00000002)
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#define INTC_CONTROL_NEWFIQAGR_SHIFT (0x00000001)
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#define INTC_CONTROL_NEWIRQAGR (0x00000001)
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#define INTC_CONTROL_NEWIRQAGR_SHIFT (0x00000000)
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/* PROTECTION */
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#define INTC_PROTECTION_PROTECTION (0x00000001u)
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#define INTC_PROTECTION_PROTECTION_SHIFT (0x00000000u)
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/* IDLE */
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#define INTC_IDLE_TURBO (0x00000002u)
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#define INTC_IDLE_TURBO_SHIFT (0x00000001u)
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#define INTC_IDLE_FUNCIDLE (0x00000001u)
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#define INTC_IDLE_FUNCIDLE_SHIFT (0x00000000u)
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/* IRQ_PRIORITY */
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#define INTC_IRQ_PRIORITY_SPURIOUSIRQFLAG (0xFFFFFFC0u)
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#define INTC_IRQ_PRIORITY_SPURIOUSIRQFLAG_SHIFT (0x00000006u)
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#define INTC_IRQ_PRIORITY_IRQPRIORITY (0x0000003Fu)
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#define INTC_IRQ_PRIORITY_IRQPRIORITY_SHIFT (0x00000000u)
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/* FIQ_PRIORITY */
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#define INTC_FIQ_PRIORITY_SPURIOUSFIQFLAG (0xFFFFFFC0u)
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#define INTC_FIQ_PRIORITY_SPURIOUSFIQFLAG_SHIFT (0x00000006u)
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#define INTC_FIQ_PRIORITY_FIQPRIORITY (0x0000003Fu)
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#define INTC_FIQ_PRIORITY_FIQPRIORITY_SHIFT (0x00000000u)
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/* THRESHOLD */
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#define INTC_THRESHOLD_PRIORITYTHRESHOLD (0x000000FFu)
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#define INTC_THRESHOLD_PRIORITYTHRESHOLD_SHIFT (0x00000000u)
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/* SICR */
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#define INTC_SICR_GLOBALMASK (0x00000040u)
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#define INTC_SICR_GLOBALMASK_SHIFT (0x00000006u)
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#define INTC_SICR_SOFTRESETINH (0x00000020u)
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#define INTC_SICR_SOFTRESETINH_SHIFT (0x00000005u)
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#define INTC_SICR_PUBLICMASKFEEDBACK (0x00000010u)
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#define INTC_SICR_PUBLICMASKFEEDBACK_SHIFT (0x00000004u)
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#define INTC_SICR_PUBLICINHIBIT (0x00000008u)
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#define INTC_SICR_PUBLICINHIBIT_SHIFT (0x00000003u)
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#define INTC_SICR_AUTOINHIBIT (0x00000004u)
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#define INTC_SICR_AUTOINHIBIT_SHIFT (0x00000002u)
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#define INTC_SICR_SSMFIQENABLE (0x00000002u)
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#define INTC_SICR_SSMFIQENABLE_SHIFT (0x00000001u)
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#define INTC_SICR_SSMFIQSTATUS (0x00000001u)
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#define INTC_SICR_SSMFIQSTATUS_SHIFT (0x00000000u)
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/* SCR0 */
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#define INTC_SCR0_SECUREENABLE (0xFFFFFFFFu)
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#define INTC_SCR0_SECUREENABLE_SHIFT (0x00000000u)
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/* SCR1 */
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#define INTC_SCR1_SECUREENABLE (0xFFFFFFFFu)
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#define INTC_SCR1_SECUREENABLE_SHIFT (0x00000000u)
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/* SCR2 */
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#define INTC_SCR2_SECUREENABLE (0xFFFFFFFFu)
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#define INTC_SCR2_SECUREENABLE_SHIFT (0x00000000u)
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/* ITR0 */
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#define INTC_ITR0_ITR (0xFFFFFFFFu)
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#define INTC_ITR0_ITR_SHIFT (0x00000000u)
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/* MIR0 */
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#define INTC_MIR0_MIR (0xFFFFFFFFu)
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#define INTC_MIR0_MIR_SHIFT (0x00000000u)
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/* MIR_CLEAR0 */
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#define INTC_MIR_CLEAR0_MIRCLEAR (0xFFFFFFFFu)
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#define INTC_MIR_CLEAR0_MIRCLEAR_SHIFT (0x00000000u)
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/* MIR_SET0 */
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#define INTC_MIR_SET0_MIRSET (0xFFFFFFFFu)
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#define INTC_MIR_SET0_MIRSET_SHIFT (0x00000000u)
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/* ISR_SET0 */
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#define INTC_ISR_SET0_ISRSET (0xFFFFFFFFu)
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#define INTC_ISR_SET0_ISRSET_SHIFT (0x00000000u)
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/* ISR_CLEAR0 */
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#define INTC_ISR_CLEAR0_ISRCLEAR (0xFFFFFFFFu)
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#define INTC_ISR_CLEAR0_ISRCLEAR_SHIFT (0x00000000u)
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/* PENDING_IRQ0 */
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#define INTC_PENDING_IRQ0_PENDING_IRQ (0xFFFFFFFFu)
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#define INTC_PENDING_IRQ0_PENDING_IRQ_SHIFT (0x00000000u)
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/* PENDING_FIQ0 */
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#define INTC_PENDING_FIQ0_PENDING_FIQ (0xFFFFFFFFu)
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#define INTC_PENDING_FIQ0_PENDING_FIQ_SHIFT (0x00000000u)
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/* ITR1 */
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#define INTC_ITR1_ITR (0xFFFFFFFFu)
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#define INTC_ITR1_ITR_SHIFT (0x00000000u)
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/* MIR1 */
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#define INTC_MIR1_MIR (0xFFFFFFFFu)
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#define INTC_MIR1_MIR_SHIFT (0x00000000u)
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/* MIR_CLEAR1 */
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#define INTC_MIR_CLEAR1_MIRCLEAR (0xFFFFFFFFu)
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#define INTC_MIR_CLEAR1_MIRCLEAR_SHIFT (0x00000000u)
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/* MIR_SET1 */
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#define INTC_MIR_SET1_MIRSET (0xFFFFFFFFu)
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#define INTC_MIR_SET1_MIRSET_SHIFT (0x00000000u)
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/* ISR_SET1 */
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#define INTC_ISR_SET1_ISRSET (0xFFFFFFFFu)
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#define INTC_ISR_SET1_ISRSET_SHIFT (0x00000000u)
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/* ISR_CLEAR1 */
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#define INTC_ISR_CLEAR1_ISRCLEAR (0xFFFFFFFFu)
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#define INTC_ISR_CLEAR1_ISRCLEAR_SHIFT (0x00000000u)
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/* PENDING_IRQ1 */
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#define INTC_PENDING_IRQ1_PENDING_IRQ (0xFFFFFFFFu)
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#define INTC_PENDING_IRQ1_PENDING_IRQ_SHIFT (0x00000000u)
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/* PENDING_FIQ1 */
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#define INTC_PENDING_FIQ1_PENDING_FIQ (0xFFFFFFFFu)
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#define INTC_PENDING_FIQ1_PENDING_FIQ_SHIFT (0x00000000u)
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/* ITR2 */
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#define INTC_ITR2_ITR (0xFFFFFFFFu)
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#define INTC_ITR2_ITR_SHIFT (0x00000000u)
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/* MIR2 */
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#define INTC_MIR2_MIR (0xFFFFFFFFu)
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#define INTC_MIR2_MIR_SHIFT (0x00000000u)
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/* MIR_CLEAR2 */
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#define INTC_MIR_CLEAR2_MIRCLEAR (0xFFFFFFFFu)
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#define INTC_MIR_CLEAR2_MIRCLEAR_SHIFT (0x00000000u)
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/* MIR_SET2 */
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#define INTC_MIR_SET2_MIRSET (0xFFFFFFFFu)
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#define INTC_MIR_SET2_MIRSET_SHIFT (0x00000000u)
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/* ISR_SET2 */
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#define INTC_ISR_SET2_ISRSET (0xFFFFFFFFu)
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#define INTC_ISR_SET2_ISRSET_SHIFT (0x00000000u)
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/* ISR_CLEAR2 */
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#define INTC_ISR_CLEAR2_ISRCLEAR (0xFFFFFFFFu)
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#define INTC_ISR_CLEAR2_ISRCLEAR_SHIFT (0x00000000u)
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/* PENDING_IRQ2 */
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#define INTC_PENDING_IRQ2_PENDING_IRQ (0xFFFFFFFFu)
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#define INTC_PENDING_IRQ2_PENDING_IRQ_SHIFT (0x00000000u)
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/* PENDING_FIQ2 */
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#define INTC_PENDING_FIQ2_PENDING_FIQ (0xFFFFFFFFu)
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#define INTC_PENDING_FIQ2_PENDING_FIQ_SHIFT (0x00000000u)
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/* ILR */
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#define INTC_ILR_PRIORITY (0x000001FCu)
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#define INTC_ILR_PRIORITY_SHIFT (0x00000002u)
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#define INTC_ILR_FIQNIRQ (0x00000001u)
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#define INTC_ILR_FIQNIRQ_SHIFT (0x00000000u)
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void rt_hw_interrupt_control(int vector, int priority, int route);
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int rt_hw_interrupt_get_active(int fiq_irq);
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void rt_hw_interrupt_ack(int fiq_irq);
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void rt_hw_interrupt_trigger(int vector);
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void rt_hw_interrupt_clear(int vector);
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#endif
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