386 lines
12 KiB
ArmAsm
386 lines
12 KiB
ArmAsm
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;==============================================================================================
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; star_rvds.s for Keil MDK 4.10
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;
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; SEP4020 start up code
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;
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; Change Logs:
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; Date Author Notes
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; 2010-03-17 zchong
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;=============================================================================================
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PMU_PLTR EQU 0x10001000 ; PLL<4C><4C><EFBFBD>ȶ<EFBFBD><C8B6><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>
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PMU_PMCR EQU 0x10001004 ; ϵͳ<CFB5><CDB3>ʱ<EFBFBD><CAB1>PLL<4C>Ŀ<EFBFBD><C4BF>ƼĴ<C6BC><C4B4><EFBFBD>
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PMU_PUCR EQU 0x10001008 ; USBʱ<42><CAB1>PLL<4C>Ŀ<EFBFBD><C4BF>ƼĴ<C6BC><C4B4><EFBFBD>
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PMU_PCSR EQU 0x1000100C ; <20>ڲ<EFBFBD>ģ<EFBFBD><C4A3>ʱ<EFBFBD><CAB1>Դ<EFBFBD><D4B4><EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF>ƼĴ<C6BC><C4B4><EFBFBD>
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PMU_PDSLOW EQU 0x10001010 ; SLOW״̬<D7B4><CCAC>ʱ<EFBFBD>ӵķ<D3B5>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD>
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PMU_PMDR EQU 0x10001014 ; оƬ<D0BE><C6AC><EFBFBD><EFBFBD>ģʽ<C4A3>Ĵ<EFBFBD><C4B4><EFBFBD>
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PMU_RCTR EQU 0x10001018 ; Reset<65><74><EFBFBD>ƼĴ<C6BC><C4B4><EFBFBD>
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PMU_CLRWAKUP EQU 0x1000101C ; WakeUp<55><70><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>
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RTC_CTR EQU 0x1000200C ; RTC<54><43><EFBFBD>ƼĴ<C6BC><C4B4><EFBFBD>
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INTC_IER EQU 0x10000000 ; IRQ<52>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>
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INTC_IMR EQU 0x10000008 ; IRQ<52>ж<EFBFBD><D0B6><EFBFBD><EFBFBD>μĴ<CEBC><C4B4><EFBFBD>
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INTC_IFSR EQU 0x10000030 ; IRQ<52>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD>״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD>
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INTC_FIER EQU 0x100000C0 ; FIQ<49>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>
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INTC_FIMR EQU 0x100000C4 ; FIQ<49>ж<EFBFBD><D0B6><EFBFBD><EFBFBD>μĴ<CEBC><C4B4><EFBFBD>
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EMI_CSACONF EQU 0x11000000 ; CSA<53><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD>
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EMI_CSECONF EQU 0x11000010 ; CSE<53><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD>
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EMI_CSFCONF EQU 0x11000014 ; CSF<53><46><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD>
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EMI_SDCONF1 EQU 0x11000018 ; SDRAMʱ<4D><CAB1><EFBFBD><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD>1
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EMI_SDCONF2 EQU 0x1100001C ; SDRAMʱ<4D><CAB1><EFBFBD><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD>2, SDRAM<41><4D>ʼ<EFBFBD><CABC><EFBFBD>õ<EFBFBD><C3B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϣ
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EMI_REMAPCONF EQU 0x11000020 ; Ƭѡ<C6AC>ռ估<D5BC><E4BCB0>ַӳ<D6B7><D3B3>REMAP<41><50><EFBFBD>üĴ<C3BC><C4B4><EFBFBD>
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Mode_USR EQU 0x10
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Mode_FIQ EQU 0x11
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Mode_IRQ EQU 0x12
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Mode_SVC EQU 0x13
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Mode_ABT EQU 0x17
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Mode_UND EQU 0x1B
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Mode_SYS EQU 0x1F
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I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
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F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
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NOINT EQU 0xc0
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MASK_MODE EQU 0x0000003F
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MODE_SVC32 EQU 0x00000013
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; Internal Memory Base Addresses
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FLASH_BASE EQU 0x20000000
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RAM_BASE EQU 0x04000000
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SDRAM_BASE EQU 0x30000000
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; Stack
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Unused_Stack_Size EQU 0x00000100
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Svc_Stack_Size EQU 0x00001000
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Abt_Stack_Size EQU 0x00000000
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Fiq_Stack_Size EQU 0x00000000
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Irq_Stack_Size EQU 0x00001000
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Usr_Stack_Size EQU 0x00000000
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;SVC STACK
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Svc_Stack SPACE Svc_Stack_Size
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__initial_sp
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Svc_Stack_Top
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;IRQ STACK
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Irq_Stack SPACE Irq_Stack_Size
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Irq_Stack_Top
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;UNUSED STACK
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Unused_Stack SPACE Unused_Stack_Size
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Unused_Stack_Top
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; Heap
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Heap_Size EQU 0x0000100
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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EXPORT Heap_Mem
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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; Area Definition and Entry Point
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; Startup Code must be linked first at Address at which it expects to run.
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AREA RESET, CODE, READONLY
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ARM
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; Exception Vectors
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; Mapped to Address 0.
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; Absolute addressing mode must be used.
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; Dummy Handlers are implemented as infinite loops which can be modified.
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EXPORT Entry_Point
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Entry_Point
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Vectors LDR PC,Reset_Addr
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LDR PC,Undef_Addr
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LDR PC,SWI_Addr
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LDR PC,PAbt_Addr
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LDR PC,DAbt_Addr
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NOP ; Reserved Vector
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LDR PC,IRQ_Addr
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LDR PC,FIQ_Addr
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Reset_Addr DCD Reset_Handler
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Undef_Addr DCD Undef_Handler
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SWI_Addr DCD SWI_Handler
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PAbt_Addr DCD PAbt_Handler
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DAbt_Addr DCD DAbt_Handler
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DCD 0 ; Reserved Address
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IRQ_Addr DCD IRQ_Handler
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FIQ_Addr DCD FIQ_Handler
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Undef_Handler B Undef_Handler
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SWI_Handler B SWI_Handler
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PAbt_Handler B Abort_Handler
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DAbt_Handler B Abort_Handler
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FIQ_Handler B FIQ_Handler
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Abort_Handler PROC
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ARM
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EXPORT Abort_Handler
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DeadLoop BHI DeadLoop ; Abort happened in irq mode, halt system.
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ENDP
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; Reset Handler
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;IMPORT __user_initial_stackheap
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EXPORT Reset_Handler
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Reset_Handler
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;****************************************************************
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;* Shutdown watchdog
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;****************************************************************
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LDR R0,=RTC_CTR
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LDR R1,=0x0
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STR R1,[R0]
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;****************************************************************
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;* shutdown interrupts
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;****************************************************************
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MRS R0, CPSR
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BIC R0, R0, #MASK_MODE
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ORR R0, R0, #MODE_SVC32
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ORR R0, R0, #I_Bit
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ORR R0, R0, #F_Bit
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MSR CPSR_c, r0
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LDR R0,=INTC_IER
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LDR R1,=0x0
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STR R1,[R0]
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LDR R0,=INTC_IMR
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LDR R1,=0xFFFFFFFF
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STR R1,[R0]
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LDR R0,=INTC_FIER
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LDR R1,=0x0
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STR R1,[R0]
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LDR R0,=INTC_FIMR
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LDR R1,=0x0F
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STR R1,[R0]
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;****************************************************************
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;* Initialize Stack Pointer
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;****************************************************************
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LDR SP, =Svc_Stack_Top ;init SP_svc
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MOV R4, #0xD2 ;chmod to irq and init SP_irq
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MSR cpsr_c, R4
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LDR SP, =Irq_Stack_Top
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MOV R4, #0XD1 ;chomod to fiq and init SP_fiq
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MSR cpsr_c, R4
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LDR SP, =Unused_Stack_Top
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MOV R4, #0XD7 ;chomod to abt and init SP_ABT
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MSR cpsr_c, R4
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LDR SP, =Unused_Stack_Top
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MOV R4, #0XDB ;chomod to undf and init SP_UNDF
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MSR cpsr_c, R4
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LDR SP, =Unused_Stack_Top
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;chomod to abt and init SP_sys
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MOV R4, #0xDF ;all interrupts disabled
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MSR cpsr_c, R4 ;SYSTEM mode, @32-bit code mode
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LDR SP, =Unused_Stack_Top
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MOV R4, #0XD3 ;chmod to svc modle, CPSR IRQ bit is disable
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MSR cpsr_c, R4
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;****************************************************************
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;* Initialize PMU & System Clock
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;****************************************************************
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LDR R4, =PMU_PCSR ; <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>ʱ<EFBFBD><CAB1>
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LDR R5, =0x0001ffff
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STR R5, [ R4 ]
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LDR R4, =PMU_PLTR ; <20><><EFBFBD><EFBFBD>PLL<4C>ȶ<EFBFBD><C8B6><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>ֵ50us*100M.
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LDR R5, =0x00fa00fa
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STR R5, [ R4 ]
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LDR R4, =PMU_PMDR ; <20><>SLOWģʽ<C4A3><CABD><EFBFBD><EFBFBD>NORMALģʽ
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LDR R5, =0x00000001
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STR R5, [ R4 ]
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LDR R4, =PMU_PMCR ; <20><><EFBFBD><EFBFBD>ϵͳʱ<CDB3><CAB1>Ϊ80MHz
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LDR R5, =0x00004009 ; 400b -- 88M
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STR R5, [ R4 ]
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;PMU_PMCR<43>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD><EFBFBD>15λ<35><CEBB>Ҫ<EFBFBD>дӵ͵<D3B5><CDB5>ߵķ<DFB5>ת<EFBFBD><D7AA><EFBFBD><EFBFBD><EFBFBD>ܴ<EFBFBD><DCB4><EFBFBD>PLL<4C><4C>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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LDR R4, =PMU_PMCR
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LDR R5, =0x0000c009
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STR R5, [ R4 ]
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;****************************************************************
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;* <20><>ʼ<EFBFBD><CABC>EMI
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;****************************************************************
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IF :DEF:INIT_EMI
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LDR R4, =EMI_CSACONF ; CSAƬѡʱ<D1A1><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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LDR R5, =0x08a6a6a1
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STR R5, [ R4 ]
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LDR R4, =EMI_CSECONF ; CSEƬѡʱ<D1A1><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C><EFBFBD><EEB1A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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LDR R5, =0x8cfffff1
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STR R5, [ R4 ]
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LDR R4, =EMI_SDCONF1 ; SDRAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1
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LDR R5, =0x1E104177
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STR R5, [ R4 ]
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LDR R4, =EMI_SDCONF2 ; SDRAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2
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LDR R5, =0x80001860
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STR R5, [ R4 ]
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ENDIF
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; Copy Exception Vectors to Internal RAM
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IF :DEF:RAM_INTVEC
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ADR R8, Vectors ; Source
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LDR R9, =RAM_BASE ; Destination
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LDMIA R8!, {R0-R7} ; Load Vectors
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STMIA R9!, {R0-R7} ; Store Vectors
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LDMIA R8!, {R0-R7} ; Load Handler Addresses
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STMIA R9!, {R0-R7} ; Store Handler Addresses
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ENDIF
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; Remap on-chip RAM to address 0
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IF :DEF:REMAP
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LDR R0, =EMI_REMAPCONF
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IF :DEF:RAM_INTVEC
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MOV R1, #0x80000000
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ELSE
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MOV R1, #0x0000000b
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ENDIF
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STR R1, [R0, #0] ; Remap
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ENDIF
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;***************************************************************
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;* Open irq interrupt
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;***************************************************************
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MRS R4, cpsr
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BIC R4, R4, #0x80 ; set bit7 to zero
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MSR cpsr_c, R4
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; Enter the C code
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IMPORT __main
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LDR R0,=__main
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BX R0
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IMPORT rt_interrupt_enter
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IMPORT rt_interrupt_leave
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IMPORT rt_thread_switch_interrupt_flag
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IMPORT rt_interrupt_from_thread
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IMPORT rt_interrupt_to_thread
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IMPORT rt_hw_trap_irq
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IRQ_Handler PROC
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EXPORT IRQ_Handler
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STMFD sp!, {r0-r12,lr}
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BL rt_interrupt_enter
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BL rt_hw_trap_irq
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BL rt_interrupt_leave
|
|||
|
|
|
|||
|
|
; if rt_thread_switch_interrupt_flag set, jump to
|
|||
|
|
; rt_hw_context_switch_interrupt_do and don't return
|
|||
|
|
LDR r0, =rt_thread_switch_interrupt_flag
|
|||
|
|
LDR r1, [r0]
|
|||
|
|
CMP r1, #1
|
|||
|
|
BEQ rt_hw_context_switch_interrupt_do
|
|||
|
|
|
|||
|
|
LDMFD sp!, {r0-r12,lr}
|
|||
|
|
SUBS pc, lr, #4
|
|||
|
|
ENDP
|
|||
|
|
|
|||
|
|
; /*
|
|||
|
|
; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
|
|||
|
|
; */
|
|||
|
|
rt_hw_context_switch_interrupt_do PROC
|
|||
|
|
EXPORT rt_hw_context_switch_interrupt_do
|
|||
|
|
MOV r1, #0 ; clear flag
|
|||
|
|
STR r1, [r0]
|
|||
|
|
|
|||
|
|
LDMFD sp!, {r0-r12,lr}; reload saved registers
|
|||
|
|
STMFD sp!, {r0-r3} ; save r0-r3
|
|||
|
|
MOV r1, sp
|
|||
|
|
ADD sp, sp, #16 ; restore sp
|
|||
|
|
SUB r2, lr, #4 ; save old task's pc to r2
|
|||
|
|
|
|||
|
|
MRS r3, spsr ; get cpsr of interrupt thread
|
|||
|
|
|
|||
|
|
; switch to SVC mode and no interrupt
|
|||
|
|
MSR cpsr_c, #I_Bit :OR F_Bit :OR Mode_SVC
|
|||
|
|
|
|||
|
|
STMFD sp!, {r2} ; push old task's pc
|
|||
|
|
STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4
|
|||
|
|
MOV r4, r1 ; Special optimised code below
|
|||
|
|
MOV r5, r3
|
|||
|
|
LDMFD r4!, {r0-r3}
|
|||
|
|
STMFD sp!, {r0-r3} ; push old task's r3-r0
|
|||
|
|
STMFD sp!, {r5} ; push old task's cpsr
|
|||
|
|
MRS r4, spsr
|
|||
|
|
STMFD sp!, {r4} ; push old task's spsr
|
|||
|
|
|
|||
|
|
LDR r4, =rt_interrupt_from_thread
|
|||
|
|
LDR r5, [r4]
|
|||
|
|
STR sp, [r5] ; store sp in preempted tasks's TCB
|
|||
|
|
|
|||
|
|
LDR r6, =rt_interrupt_to_thread
|
|||
|
|
LDR r6, [r6]
|
|||
|
|
LDR sp, [r6] ; get new task's stack pointer
|
|||
|
|
|
|||
|
|
LDMFD sp!, {r4} ; pop new task's spsr
|
|||
|
|
MSR spsr_cxsf, r4
|
|||
|
|
LDMFD sp!, {r4} ; pop new task's psr
|
|||
|
|
MSR cpsr_cxsf, r4
|
|||
|
|
|
|||
|
|
LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc
|
|||
|
|
ENDP
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
ALIGN
|
|||
|
|
IF :DEF:__MICROLIB
|
|||
|
|
|
|||
|
|
EXPORT __heap_base
|
|||
|
|
EXPORT __heap_limit
|
|||
|
|
EXPORT __initial_sp
|
|||
|
|
|
|||
|
|
ELSE ;__MICROLIB
|
|||
|
|
; User Initial Stack & Heap
|
|||
|
|
AREA |.text|, CODE, READONLY
|
|||
|
|
|
|||
|
|
IMPORT __use_two_region_memory
|
|||
|
|
EXPORT __user_initial_stackheap
|
|||
|
|
__user_initial_stackheap
|
|||
|
|
|
|||
|
|
LDR R0, = Heap_Mem
|
|||
|
|
LDR R1, = (Svc_Stack + Svc_Stack_Size)
|
|||
|
|
LDR R2, = (Heap_Mem + Heap_Size)
|
|||
|
|
LDR R3, = Svc_Stack
|
|||
|
|
BX LR
|
|||
|
|
ALIGN
|
|||
|
|
ENDIF
|
|||
|
|
END
|