334 lines
11 KiB
C
334 lines
11 KiB
C
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/******************************************************************************
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* @file mpu_armv8.h
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* @brief CMSIS MPU API for Armv8-M MPU
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* @version V5.0.4
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* @date 10. January 2018
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******************************************************************************/
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/*
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* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#if defined ( __ICCARM__ )
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#pragma system_include /* treat file as system include file for MISRA check */
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#elif defined (__clang__)
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#pragma clang system_header /* treat file as system include file */
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#endif
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#ifndef ARM_MPU_ARMV8_H
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#define ARM_MPU_ARMV8_H
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/** \brief Attribute for device memory (outer only) */
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#define ARM_MPU_ATTR_DEVICE ( 0U )
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/** \brief Attribute for non-cacheable, normal memory */
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#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
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/** \brief Attribute for normal memory (outer and inner)
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* \param NT Non-Transient: Set to 1 for non-transient data.
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* \param WB Write-Back: Set to 1 to use write-back update policy.
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* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
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* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
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*/
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#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
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(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
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/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
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#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
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/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
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#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
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/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
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#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
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/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
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#define ARM_MPU_ATTR_DEVICE_GRE (3U)
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/** \brief Memory Attribute
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* \param O Outer memory attributes
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* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
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*/
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#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
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/** \brief Normal memory non-shareable */
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#define ARM_MPU_SH_NON (0U)
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/** \brief Normal memory outer shareable */
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#define ARM_MPU_SH_OUTER (2U)
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/** \brief Normal memory inner shareable */
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#define ARM_MPU_SH_INNER (3U)
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/** \brief Memory access permissions
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* \param RO Read-Only: Set to 1 for read-only memory.
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* \param NP Non-Privileged: Set to 1 for non-privileged memory.
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*/
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#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
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/** \brief Region Base Address Register value
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* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
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* \param SH Defines the Shareability domain for this memory region.
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* \param RO Read-Only: Set to 1 for a read-only memory region.
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* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
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* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
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*/
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#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
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((BASE & MPU_RBAR_BASE_Msk) | \
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((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
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((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
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((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
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/** \brief Region Limit Address Register value
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* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
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* \param IDX The attribute index to be associated with this memory region.
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*/
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#define ARM_MPU_RLAR(LIMIT, IDX) \
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((LIMIT & MPU_RLAR_LIMIT_Msk) | \
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((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
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(MPU_RLAR_EN_Msk))
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/**
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* Struct for a single MPU Region
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*/
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typedef struct {
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uint32_t RBAR; /*!< Region Base Address Register value */
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uint32_t RLAR; /*!< Region Limit Address Register value */
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} ARM_MPU_Region_t;
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/** Enable the MPU.
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* \param MPU_Control Default access permissions for unconfigured regions.
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*/
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__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
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{
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__DSB();
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__ISB();
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MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
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#ifdef SCB_SHCSR_MEMFAULTENA_Msk
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SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
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#endif
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}
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/** Disable the MPU.
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*/
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__STATIC_INLINE void ARM_MPU_Disable(void)
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{
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__DSB();
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__ISB();
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#ifdef SCB_SHCSR_MEMFAULTENA_Msk
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SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
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#endif
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MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
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}
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#ifdef MPU_NS
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/** Enable the Non-secure MPU.
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* \param MPU_Control Default access permissions for unconfigured regions.
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*/
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__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
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{
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__DSB();
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__ISB();
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MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
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#ifdef SCB_SHCSR_MEMFAULTENA_Msk
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SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
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#endif
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}
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/** Disable the Non-secure MPU.
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*/
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__STATIC_INLINE void ARM_MPU_Disable_NS(void)
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{
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__DSB();
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__ISB();
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#ifdef SCB_SHCSR_MEMFAULTENA_Msk
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SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
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#endif
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MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
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}
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#endif
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/** Set the memory attribute encoding to the given MPU.
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* \param mpu Pointer to the MPU to be configured.
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* \param idx The attribute index to be set [0-7]
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* \param attr The attribute value to be set.
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*/
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__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
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{
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const uint8_t reg = idx / 4U;
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const uint32_t pos = ((idx % 4U) * 8U);
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const uint32_t mask = 0xFFU << pos;
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if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
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return; // invalid index
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}
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mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
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}
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/** Set the memory attribute encoding.
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* \param idx The attribute index to be set [0-7]
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* \param attr The attribute value to be set.
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*/
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__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
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{
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ARM_MPU_SetMemAttrEx(MPU, idx, attr);
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}
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#ifdef MPU_NS
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/** Set the memory attribute encoding to the Non-secure MPU.
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* \param idx The attribute index to be set [0-7]
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* \param attr The attribute value to be set.
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*/
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__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
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{
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ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
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}
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#endif
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/** Clear and disable the given MPU region of the given MPU.
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* \param mpu Pointer to MPU to be used.
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* \param rnr Region number to be cleared.
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*/
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__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
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{
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mpu->RNR = rnr;
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mpu->RLAR = 0U;
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}
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/** Clear and disable the given MPU region.
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* \param rnr Region number to be cleared.
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*/
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__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
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{
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ARM_MPU_ClrRegionEx(MPU, rnr);
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}
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#ifdef MPU_NS
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/** Clear and disable the given Non-secure MPU region.
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* \param rnr Region number to be cleared.
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*/
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__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
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{
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ARM_MPU_ClrRegionEx(MPU_NS, rnr);
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}
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#endif
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/** Configure the given MPU region of the given MPU.
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* \param mpu Pointer to MPU to be used.
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* \param rnr Region number to be configured.
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* \param rbar Value for RBAR register.
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* \param rlar Value for RLAR register.
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*/
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__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
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{
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mpu->RNR = rnr;
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mpu->RBAR = rbar;
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mpu->RLAR = rlar;
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}
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/** Configure the given MPU region.
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* \param rnr Region number to be configured.
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* \param rbar Value for RBAR register.
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* \param rlar Value for RLAR register.
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*/
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__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
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{
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ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
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}
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#ifdef MPU_NS
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/** Configure the given Non-secure MPU region.
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* \param rnr Region number to be configured.
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* \param rbar Value for RBAR register.
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* \param rlar Value for RLAR register.
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*/
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__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
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{
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ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
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}
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#endif
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/** Memcopy with strictly ordered memory access, e.g. for register targets.
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* \param dst Destination data is copied to.
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* \param src Source data is copied from.
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* \param len Amount of data words to be copied.
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*/
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__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
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{
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uint32_t i;
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for (i = 0U; i < len; ++i)
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{
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dst[i] = src[i];
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}
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}
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/** Load the given number of MPU regions from a table to the given MPU.
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* \param mpu Pointer to the MPU registers to be used.
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* \param rnr First region number to be configured.
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* \param table Pointer to the MPU configuration table.
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* \param cnt Amount of regions to be configured.
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*/
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__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
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{
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const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
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if (cnt == 1U) {
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mpu->RNR = rnr;
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orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
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} else {
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uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
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uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
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mpu->RNR = rnrBase;
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while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
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uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
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orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
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table += c;
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cnt -= c;
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rnrOffset = 0U;
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rnrBase += MPU_TYPE_RALIASES;
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mpu->RNR = rnrBase;
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}
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orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
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}
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}
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/** Load the given number of MPU regions from a table.
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* \param rnr First region number to be configured.
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* \param table Pointer to the MPU configuration table.
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* \param cnt Amount of regions to be configured.
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*/
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__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
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{
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ARM_MPU_LoadEx(MPU, rnr, table, cnt);
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}
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#ifdef MPU_NS
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/** Load the given number of MPU regions from a table to the Non-secure MPU.
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* \param rnr First region number to be configured.
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* \param table Pointer to the MPU configuration table.
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* \param cnt Amount of regions to be configured.
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*/
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__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
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{
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ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
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}
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#endif
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#endif
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