465 lines
15 KiB
ArmAsm
465 lines
15 KiB
ArmAsm
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;/*****************************************************************************/
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;/* STARTUP.S: Startup file for Philips LPC2000 */
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;/*****************************************************************************/
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;/* <<< Use Configuration Wizard in Context Menu >>> */
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;/*****************************************************************************/
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;/* This file is part of the uVision/ARM development tools. */
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;/* Copyright (c) 2005-2007 Keil Software. All rights reserved. */
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;/* This software may only be used under the terms of a valid, current, */
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;/* end user licence from KEIL for a compatible version of KEIL software */
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;/* development tools. Nothing else gives you the right to use this software. */
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;/*****************************************************************************/
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;/*
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; * The STARTUP.S code is executed after CPU Reset. This file may be
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; * translated with the following SET symbols. In uVision these SET
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; * symbols are entered under Options - ASM - Define.
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; *
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; * REMAP: when set the startup code initializes the register MEMMAP
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; * which overwrites the settings of the CPU configuration pins. The
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; * startup and interrupt vectors are remapped from:
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; * 0x00000000 default setting (not remapped)
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; * 0x80000000 when EXTMEM_MODE is used
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; * 0x40000000 when RAM_MODE is used
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; *
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; * EXTMEM_MODE: when set the device is configured for code execution
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; * from external memory starting at address 0x80000000.
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; *
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; * RAM_MODE: when set the device is configured for code execution
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; * from on-chip RAM starting at address 0x40000000.
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; *
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; * EXTERNAL_MODE: when set the PIN2SEL values are written that enable
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; * the external BUS at startup.
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; */
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; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
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Mode_USR EQU 0x10
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Mode_FIQ EQU 0x11
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Mode_IRQ EQU 0x12
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Mode_SVC EQU 0x13
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Mode_ABT EQU 0x17
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Mode_UND EQU 0x1B
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Mode_SYS EQU 0x1F
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I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
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F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
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;// <h> Stack Configuration (Stack Sizes in Bytes)
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;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
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;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
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;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
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;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
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;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
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;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
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;// </h>
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UND_Stack_Size EQU 0x00000000
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SVC_Stack_Size EQU 0x00000100
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ABT_Stack_Size EQU 0x00000000
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FIQ_Stack_Size EQU 0x00000000
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IRQ_Stack_Size EQU 0x00000100
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USR_Stack_Size EQU 0x00000100
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ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
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FIQ_Stack_Size + IRQ_Stack_Size)
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE USR_Stack_Size
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__initial_sp SPACE ISR_Stack_Size
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Stack_Top
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;// <h> Heap Configuration
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;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
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;// </h>
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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; VPBDIV definitions
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VPBDIV EQU 0xE01FC100 ; VPBDIV Address
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;// <e> VPBDIV Setup
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;// <i> Peripheral Bus Clock Rate
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;// <o1.0..1> VPBDIV: VPB Clock
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;// <0=> VPB Clock = CPU Clock / 4
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;// <1=> VPB Clock = CPU Clock
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;// <2=> VPB Clock = CPU Clock / 2
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;// <o1.4..5> XCLKDIV: XCLK Pin
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;// <0=> XCLK Pin = CPU Clock / 4
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;// <1=> XCLK Pin = CPU Clock
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;// <2=> XCLK Pin = CPU Clock / 2
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;// </e>
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VPBDIV_SETUP EQU 0
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VPBDIV_Val EQU 0x00000000
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; Phase Locked Loop (PLL) definitions
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PLL_BASE EQU 0xE01FC080 ; PLL Base Address
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PLLCON_OFS EQU 0x00 ; PLL Control Offset
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PLLCFG_OFS EQU 0x04 ; PLL Configuration Offset
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PLLSTAT_OFS EQU 0x08 ; PLL Status Offset
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PLLFEED_OFS EQU 0x0C ; PLL Feed Offset
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PLLCON_PLLE EQU (1<<0) ; PLL Enable
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PLLCON_PLLC EQU (1<<1) ; PLL Connect
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PLLCFG_MSEL EQU (0x1F<<0) ; PLL Multiplier
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PLLCFG_PSEL EQU (0x03<<5) ; PLL Divider
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PLLSTAT_PLOCK EQU (1<<10) ; PLL Lock Status
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;// <e> PLL Setup
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;// <o1.0..4> MSEL: PLL Multiplier Selection
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;// <1-32><#-1>
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;// <i> M Value
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;// <o1.5..6> PSEL: PLL Divider Selection
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;// <0=> 1 <1=> 2 <2=> 4 <3=> 8
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;// <i> P Value
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;// </e>
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PLL_SETUP EQU 1
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PLLCFG_Val EQU 0x00000024
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; Memory Accelerator Module (MAM) definitions
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MAM_BASE EQU 0xE01FC000 ; MAM Base Address
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MAMCR_OFS EQU 0x00 ; MAM Control Offset
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MAMTIM_OFS EQU 0x04 ; MAM Timing Offset
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;// <e> MAM Setup
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;// <o1.0..1> MAM Control
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;// <0=> Disabled
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;// <1=> Partially Enabled
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;// <2=> Fully Enabled
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;// <i> Mode
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;// <o2.0..2> MAM Timing
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;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3
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;// <4=> 4 <5=> 5 <6=> 6 <7=> 7
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;// <i> Fetch Cycles
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;// </e>
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MAM_SETUP EQU 1
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MAMCR_Val EQU 0x00000002
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MAMTIM_Val EQU 0x00000004
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; External Memory Controller (EMC) definitions
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EMC_BASE EQU 0xFFE00000 ; EMC Base Address
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BCFG0_OFS EQU 0x00 ; BCFG0 Offset
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BCFG1_OFS EQU 0x04 ; BCFG1 Offset
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BCFG2_OFS EQU 0x08 ; BCFG2 Offset
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BCFG3_OFS EQU 0x0C ; BCFG3 Offset
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;// <e> External Memory Controller (EMC)
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EMC_SETUP EQU 0
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;// <e> Bank Configuration 0 (BCFG0)
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;// <o1.0..3> IDCY: Idle Cycles <0-15>
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;// <o1.5..9> WST1: Wait States 1 <0-31>
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;// <o1.11..15> WST2: Wait States 2 <0-31>
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;// <o1.10> RBLE: Read Byte Lane Enable
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;// <o1.26> WP: Write Protect
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;// <o1.27> BM: Burst ROM
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;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
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;// <2=> 32-bit <3=> Reserved
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;// </e>
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BCFG0_SETUP EQU 0
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BCFG0_Val EQU 0x0000FBEF
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;// <e> Bank Configuration 1 (BCFG1)
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;// <o1.0..3> IDCY: Idle Cycles <0-15>
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;// <o1.5..9> WST1: Wait States 1 <0-31>
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;// <o1.11..15> WST2: Wait States 2 <0-31>
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;// <o1.10> RBLE: Read Byte Lane Enable
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;// <o1.26> WP: Write Protect
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;// <o1.27> BM: Burst ROM
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;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
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;// <2=> 32-bit <3=> Reserved
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;// </e>
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BCFG1_SETUP EQU 0
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BCFG1_Val EQU 0x0000FBEF
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;// <e> Bank Configuration 2 (BCFG2)
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;// <o1.0..3> IDCY: Idle Cycles <0-15>
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;// <o1.5..9> WST1: Wait States 1 <0-31>
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;// <o1.11..15> WST2: Wait States 2 <0-31>
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;// <o1.10> RBLE: Read Byte Lane Enable
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;// <o1.26> WP: Write Protect
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;// <o1.27> BM: Burst ROM
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;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
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;// <2=> 32-bit <3=> Reserved
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;// </e>
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BCFG2_SETUP EQU 0
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BCFG2_Val EQU 0x0000FBEF
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;// <e> Bank Configuration 3 (BCFG3)
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;// <o1.0..3> IDCY: Idle Cycles <0-15>
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;// <o1.5..9> WST1: Wait States 1 <0-31>
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;// <o1.11..15> WST2: Wait States 2 <0-31>
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;// <o1.10> RBLE: Read Byte Lane Enable
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;// <o1.26> WP: Write Protect
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;// <o1.27> BM: Burst ROM
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;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
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;// <2=> 32-bit <3=> Reserved
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;// </e>
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BCFG3_SETUP EQU 0
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BCFG3_Val EQU 0x0000FBEF
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;// </e> End of EMC
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; External Memory Pins definitions
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PINSEL2 EQU 0xE002C014 ; PINSEL2 Address
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PINSEL2_Val EQU 0x0E6149E4 ; CS0..3, OE, WE, BLS0..3,
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; D0..31, A2..23, JTAG Pins
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PRESERVE8
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; Area Definition and Entry Point
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; Startup Code must be linked first at Address at which it expects to run.
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AREA RESET, CODE, READONLY
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ARM
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; Exception Vectors
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; Mapped to Address 0.
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; Absolute addressing mode must be used.
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; Dummy Handlers are implemented as infinite loops which can be modified.
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Vectors LDR PC, Reset_Addr
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LDR PC, Undef_Addr
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LDR PC, SWI_Addr
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LDR PC, PAbt_Addr
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LDR PC, DAbt_Addr
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NOP ; Reserved Vector
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LDR PC, IRQ_Addr
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LDR PC, FIQ_Addr
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Reset_Addr DCD Reset_Handler
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Undef_Addr DCD Undef_Handler
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SWI_Addr DCD SWI_Handler
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PAbt_Addr DCD PAbt_Handler
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DAbt_Addr DCD DAbt_Handler
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DCD 0 ; Reserved Address
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IRQ_Addr DCD IRQ_Handler
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FIQ_Addr DCD FIQ_Handler
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Undef_Handler B Undef_Handler
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SWI_Handler B SWI_Handler
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PAbt_Handler B PAbt_Handler
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DAbt_Handler B DAbt_Handler
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FIQ_Handler B FIQ_Handler
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; Reset Handler
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EXPORT Reset_Handler
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Reset_Handler
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; Setup External Memory Pins
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IF :DEF:EXTERNAL_MODE
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LDR R0, =PINSEL2
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LDR R1, =PINSEL2_Val
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STR R1, [R0]
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ENDIF
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; Setup External Memory Controller
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IF EMC_SETUP <> 0
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LDR R0, =EMC_BASE
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IF BCFG0_SETUP <> 0
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LDR R1, =BCFG0_Val
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STR R1, [R0, #BCFG0_OFS]
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ENDIF
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IF BCFG1_SETUP <> 0
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LDR R1, =BCFG1_Val
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STR R1, [R0, #BCFG1_OFS]
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ENDIF
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IF BCFG2_SETUP <> 0
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LDR R1, =BCFG2_Val
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STR R1, [R0, #BCFG2_OFS]
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ENDIF
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IF BCFG3_SETUP <> 0
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LDR R1, =BCFG3_Val
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STR R1, [R0, #BCFG3_OFS]
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ENDIF
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ENDIF ; EMC_SETUP
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; Setup VPBDIV
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IF VPBDIV_SETUP <> 0
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LDR R0, =VPBDIV
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LDR R1, =VPBDIV_Val
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STR R1, [R0]
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ENDIF
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; Setup PLL
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IF PLL_SETUP <> 0
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LDR R0, =PLL_BASE
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MOV R1, #0xAA
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MOV R2, #0x55
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; Configure and Enable PLL
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MOV R3, #PLLCFG_Val
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STR R3, [R0, #PLLCFG_OFS]
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MOV R3, #PLLCON_PLLE
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STR R3, [R0, #PLLCON_OFS]
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STR R1, [R0, #PLLFEED_OFS]
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STR R2, [R0, #PLLFEED_OFS]
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; Wait until PLL Locked
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PLL_Loop LDR R3, [R0, #PLLSTAT_OFS]
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ANDS R3, R3, #PLLSTAT_PLOCK
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BEQ PLL_Loop
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; Switch to PLL Clock
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MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC)
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STR R3, [R0, #PLLCON_OFS]
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STR R1, [R0, #PLLFEED_OFS]
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STR R2, [R0, #PLLFEED_OFS]
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ENDIF ; PLL_SETUP
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; Setup MAM
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IF MAM_SETUP <> 0
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LDR R0, =MAM_BASE
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MOV R1, #MAMTIM_Val
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STR R1, [R0, #MAMTIM_OFS]
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MOV R1, #MAMCR_Val
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STR R1, [R0, #MAMCR_OFS]
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ENDIF ; MAM_SETUP
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||
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|
||
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|
||
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|
; Memory Mapping (when Interrupt Vectors are in RAM)
|
||
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|
MEMMAP EQU 0xE01FC040 ; Memory Mapping Control
|
||
|
|
IF :DEF:REMAP
|
||
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LDR R0, =MEMMAP
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||
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|
IF :DEF:EXTMEM_MODE
|
||
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MOV R1, #3
|
||
|
|
ELIF :DEF:RAM_MODE
|
||
|
|
MOV R1, #2
|
||
|
|
ELSE
|
||
|
|
MOV R1, #1
|
||
|
|
ENDIF
|
||
|
|
STR R1, [R0]
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
|
||
|
|
; Initialise Interrupt System
|
||
|
|
; ...
|
||
|
|
|
||
|
|
|
||
|
|
; Setup Stack for each mode
|
||
|
|
|
||
|
|
LDR R0, =Stack_Top
|
||
|
|
|
||
|
|
; Enter Undefined Instruction Mode and set its Stack Pointer
|
||
|
|
MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
|
||
|
|
MOV SP, R0
|
||
|
|
SUB R0, R0, #UND_Stack_Size
|
||
|
|
|
||
|
|
; Enter Abort Mode and set its Stack Pointer
|
||
|
|
MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
|
||
|
|
MOV SP, R0
|
||
|
|
SUB R0, R0, #ABT_Stack_Size
|
||
|
|
|
||
|
|
; Enter FIQ Mode and set its Stack Pointer
|
||
|
|
MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
|
||
|
|
MOV SP, R0
|
||
|
|
SUB R0, R0, #FIQ_Stack_Size
|
||
|
|
|
||
|
|
; Enter IRQ Mode and set its Stack Pointer
|
||
|
|
MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
|
||
|
|
MOV SP, R0
|
||
|
|
SUB R0, R0, #IRQ_Stack_Size
|
||
|
|
|
||
|
|
; Enter Supervisor Mode and set its Stack Pointer
|
||
|
|
MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
|
||
|
|
MOV SP, R0
|
||
|
|
; SUB R0, R0, #SVC_Stack_Size
|
||
|
|
|
||
|
|
; Enter User Mode and set its Stack Pointer
|
||
|
|
; RT-Thread does not use user mode
|
||
|
|
; MSR CPSR_c, #Mode_USR
|
||
|
|
IF :DEF:__MICROLIB
|
||
|
|
|
||
|
|
EXPORT __initial_sp
|
||
|
|
|
||
|
|
ELSE
|
||
|
|
|
||
|
|
; MOV SP, R0
|
||
|
|
; SUB SL, SP, #USR_Stack_Size
|
||
|
|
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
; Enter the C code
|
||
|
|
|
||
|
|
IMPORT __main
|
||
|
|
LDR R0, =__main
|
||
|
|
BX R0
|
||
|
|
|
||
|
|
IMPORT rt_interrupt_enter
|
||
|
|
IMPORT rt_interrupt_leave
|
||
|
|
IMPORT rt_thread_switch_interrupt_flag
|
||
|
|
IMPORT rt_interrupt_from_thread
|
||
|
|
IMPORT rt_interrupt_to_thread
|
||
|
|
IMPORT rt_hw_trap_irq
|
||
|
|
IMPORT rt_hw_context_switch_interrupt_do
|
||
|
|
|
||
|
|
IRQ_Handler PROC
|
||
|
|
EXPORT IRQ_Handler
|
||
|
|
STMFD sp!, {r0-r12,lr}
|
||
|
|
BL rt_interrupt_enter
|
||
|
|
BL rt_hw_trap_irq
|
||
|
|
BL rt_interrupt_leave
|
||
|
|
|
||
|
|
; if rt_thread_switch_interrupt_flag set, jump to
|
||
|
|
; rt_hw_context_switch_interrupt_do and don't return
|
||
|
|
LDR r0, =rt_thread_switch_interrupt_flag
|
||
|
|
LDR r1, [r0]
|
||
|
|
CMP r1, #1
|
||
|
|
BEQ rt_hw_context_switch_interrupt_do
|
||
|
|
|
||
|
|
LDMFD sp!, {r0-r12,lr}
|
||
|
|
SUBS pc, lr, #4
|
||
|
|
ENDP
|
||
|
|
|
||
|
|
IF :DEF:__MICROLIB
|
||
|
|
|
||
|
|
EXPORT __heap_base
|
||
|
|
EXPORT __heap_limit
|
||
|
|
|
||
|
|
ELSE
|
||
|
|
; User Initial Stack & Heap
|
||
|
|
AREA |.text|, CODE, READONLY
|
||
|
|
|
||
|
|
IMPORT __use_two_region_memory
|
||
|
|
EXPORT __user_initial_stackheap
|
||
|
|
__user_initial_stackheap
|
||
|
|
|
||
|
|
LDR R0, = Heap_Mem
|
||
|
|
LDR R1, =(Stack_Mem + USR_Stack_Size)
|
||
|
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||
|
|
LDR R3, = Stack_Mem
|
||
|
|
BX LR
|
||
|
|
ENDIF
|
||
|
|
|
||
|
|
END
|