564 lines
16 KiB
C
564 lines
16 KiB
C
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2011-10-21 Bernard the first version.
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* 2011-10-27 aozima update for cortex-M4 FPU.
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* 2011-12-31 aozima fixed stack align issues.
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* 2012-01-01 aozima support context switch load/store FPU register.
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* 2012-12-11 lgnq fixed the coding style.
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* 2012-12-23 aozima stack addr align to 8byte.
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* 2012-12-29 Bernard Add exception hook.
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* 2013-06-23 aozima support lazy stack optimized.
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* 2018-07-24 aozima enhancement hard fault exception handler.
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* 2019-07-03 yangjie add __rt_ffs() for armclang.
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*/
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#include <rtthread.h>
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#if /* ARMCC */ ( (defined ( __CC_ARM ) && defined ( __TARGET_FPU_VFP )) \
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/* Clang */ || (defined ( __clang__ ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) \
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/* IAR */ || (defined ( __ICCARM__ ) && defined ( __ARMVFP__ )) \
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/* GNU */ || (defined ( __GNUC__ ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) )
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#define USE_FPU 1
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#else
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#define USE_FPU 0
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#endif
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/* exception and interrupt handler table */
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rt_uint32_t rt_interrupt_from_thread;
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rt_uint32_t rt_interrupt_to_thread;
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rt_uint32_t rt_thread_switch_interrupt_flag;
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/* exception hook */
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static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL;
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struct exception_stack_frame
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{
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rt_uint32_t r0;
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rt_uint32_t r1;
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rt_uint32_t r2;
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rt_uint32_t r3;
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rt_uint32_t r12;
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rt_uint32_t lr;
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rt_uint32_t pc;
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rt_uint32_t psr;
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};
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struct stack_frame
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{
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rt_uint32_t tz;
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rt_uint32_t lr;
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rt_uint32_t psplim;
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rt_uint32_t control;
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/* r4 ~ r11 register */
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rt_uint32_t r4;
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rt_uint32_t r5;
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rt_uint32_t r6;
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rt_uint32_t r7;
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rt_uint32_t r8;
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rt_uint32_t r9;
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rt_uint32_t r10;
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rt_uint32_t r11;
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struct exception_stack_frame exception_stack_frame;
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};
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struct exception_stack_frame_fpu
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{
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rt_uint32_t r0;
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rt_uint32_t r1;
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rt_uint32_t r2;
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rt_uint32_t r3;
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rt_uint32_t r12;
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rt_uint32_t lr;
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rt_uint32_t pc;
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rt_uint32_t psr;
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#if USE_FPU
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/* FPU register */
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rt_uint32_t S0;
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rt_uint32_t S1;
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rt_uint32_t S2;
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rt_uint32_t S3;
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rt_uint32_t S4;
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rt_uint32_t S5;
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rt_uint32_t S6;
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rt_uint32_t S7;
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rt_uint32_t S8;
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rt_uint32_t S9;
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rt_uint32_t S10;
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rt_uint32_t S11;
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rt_uint32_t S12;
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rt_uint32_t S13;
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rt_uint32_t S14;
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rt_uint32_t S15;
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rt_uint32_t FPSCR;
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rt_uint32_t NO_NAME;
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#endif
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};
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struct stack_frame_fpu
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{
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rt_uint32_t flag;
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/* r4 ~ r11 register */
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rt_uint32_t r4;
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rt_uint32_t r5;
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rt_uint32_t r6;
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rt_uint32_t r7;
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rt_uint32_t r8;
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rt_uint32_t r9;
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rt_uint32_t r10;
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rt_uint32_t r11;
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#if USE_FPU
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/* FPU register s16 ~ s31 */
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rt_uint32_t s16;
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rt_uint32_t s17;
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rt_uint32_t s18;
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rt_uint32_t s19;
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rt_uint32_t s20;
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rt_uint32_t s21;
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rt_uint32_t s22;
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rt_uint32_t s23;
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rt_uint32_t s24;
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rt_uint32_t s25;
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rt_uint32_t s26;
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rt_uint32_t s27;
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rt_uint32_t s28;
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rt_uint32_t s29;
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rt_uint32_t s30;
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rt_uint32_t s31;
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#endif
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struct exception_stack_frame_fpu exception_stack_frame;
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};
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rt_uint8_t *rt_hw_stack_init(void *tentry,
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void *parameter,
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rt_uint8_t *stack_addr,
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void *texit)
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{
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struct stack_frame *stack_frame;
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rt_uint8_t *stk;
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unsigned long i;
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stk = stack_addr + sizeof(rt_uint32_t);
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stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8);
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stk -= sizeof(struct stack_frame);
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stack_frame = (struct stack_frame *)stk;
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/* init all register */
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for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++)
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{
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((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef;
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}
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stack_frame->exception_stack_frame.r0 = (unsigned long)parameter; /* r0 : argument */
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stack_frame->exception_stack_frame.r1 = 0; /* r1 */
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stack_frame->exception_stack_frame.r2 = 0; /* r2 */
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stack_frame->exception_stack_frame.r3 = 0; /* r3 */
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stack_frame->exception_stack_frame.r12 = 0; /* r12 */
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stack_frame->exception_stack_frame.lr = (unsigned long)texit; /* lr */
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stack_frame->exception_stack_frame.pc = (unsigned long)tentry; /* entry point, pc */
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stack_frame->exception_stack_frame.psr = 0x01000000L; /* PSR */
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stack_frame->tz = 0x00; /* trustzone thread context */
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/*
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* Exception return behavior
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* +--------+---+---+------+-------+------+-------+---+----+
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* | PREFIX | - | S | DCRS | FType | Mode | SPSEL | - | ES |
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* +--------+---+---+------+-------+------+-------+---+----+
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* PREFIX [31:24] - Indicates that this is an EXC_RETURN value. This field reads as 0b11111111.
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* S [6] - Indicates whether registers have been pushed to a Secure or Non-secure stack.
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* 0: Non-secure stack used.
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* 1: Secure stack used.
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* DCRS [5] - Indicates whether the default stacking rules apply, or whether the callee registers are already on the stack.
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* 0: Stacking of the callee saved registers is skipped.
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* 1: Default rules for stacking the callee registers are followed.
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* FType [4] - In a PE with the Main and Floating-point Extensions:
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* 0: The PE allocated space on the stack for FP context.
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* 1: The PE did not allocate space on the stack for FP context.
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* In a PE without the Floating-point Extension, this bit is Reserved, RES1.
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* Mode [3] - Indicates the mode that was stacked from.
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* 0: Handler mode.
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* 1: Thread mode.
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* SPSEL [2] - Indicates which stack contains the exception stack frame.
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* 0: Main stack pointer.
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* 1: Process stack pointer.
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* ES [0] - Indicates the Security state the exception was taken to.
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* 0: Non-secure.
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* 1: Secure.
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*/
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#ifdef ARCH_ARM_CORTEX_SECURE
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stack_frame->lr = 0xfffffffdL;
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#else
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stack_frame->lr = 0xffffffbcL;
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#endif
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stack_frame->psplim = 0x00;
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/*
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* CONTROL register bit assignments
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* +---+------+------+-------+-------+
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* | - | SFPA | FPCA | SPSEL | nPRIV |
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* +---+------+------+-------+-------+
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* SFPA [3] - Indicates that the floating-point registers contain active state that belongs to the Secure state:
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* 0: The floating-point registers do not contain state that belongs to the Secure state.
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* 1: The floating-point registers contain state that belongs to the Secure state.
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* This bit is not banked between Security states and RAZ/WI from Non-secure state.
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* FPCA [2] - Indicates whether floating-point context is active:
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* 0: No floating-point context active.
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* 1: Floating-point context active.
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* This bit is used to determine whether to preserve floating-point state when processing an exception.
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* This bit is not banked between Security states.
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* SPSEL [1] - Defines the currently active stack pointer:
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* 0: MSP is the current stack pointer.
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* 1: PSP is the current stack pointer.
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* In Handler mode, this bit reads as zero and ignores writes. The CortexM33 core updates this bit automatically onexception return.
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* This bit is banked between Security states.
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* nPRIV [0] - Defines the Thread mode privilege level:
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* 0: Privileged.
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* 1: Unprivileged.
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* This bit is banked between Security states.
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*
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*/
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stack_frame->control = 0x00000000L;
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/* return task's current stack address */
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return stk;
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}
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/**
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* This function set the hook, which is invoked on fault exception handling.
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*
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* @param exception_handle the exception handling hook function.
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*/
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void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context))
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{
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rt_exception_hook = exception_handle;
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}
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#define SCB_CFSR (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */
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#define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */
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#define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */
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#define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */
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#define SCB_AIRCR (*(volatile unsigned long *)0xE000ED0C) /* Reset control Address Register */
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#define SCB_RESET_VALUE 0x05FA0004 /* Reset value, write to SCB_AIRCR can reset cpu */
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#define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */
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#define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */
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#define SCB_CFSR_UFSR (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */
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#ifdef RT_USING_FINSH
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static void usage_fault_track(void)
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{
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rt_kprintf("usage fault:\n");
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rt_kprintf("SCB_CFSR_UFSR:0x%02X ", SCB_CFSR_UFSR);
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if(SCB_CFSR_UFSR & (1<<0))
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{
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/* [0]:UNDEFINSTR */
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rt_kprintf("UNDEFINSTR ");
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}
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if(SCB_CFSR_UFSR & (1<<1))
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{
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/* [1]:INVSTATE */
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rt_kprintf("INVSTATE ");
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}
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if(SCB_CFSR_UFSR & (1<<2))
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{
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/* [2]:INVPC */
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rt_kprintf("INVPC ");
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}
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if(SCB_CFSR_UFSR & (1<<3))
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{
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/* [3]:NOCP */
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rt_kprintf("NOCP ");
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}
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if(SCB_CFSR_UFSR & (1<<8))
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{
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/* [8]:UNALIGNED */
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rt_kprintf("UNALIGNED ");
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}
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if(SCB_CFSR_UFSR & (1<<9))
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{
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/* [9]:DIVBYZERO */
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rt_kprintf("DIVBYZERO ");
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}
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rt_kprintf("\n");
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}
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static void bus_fault_track(void)
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{
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rt_kprintf("bus fault:\n");
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rt_kprintf("SCB_CFSR_BFSR:0x%02X ", SCB_CFSR_BFSR);
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if(SCB_CFSR_BFSR & (1<<0))
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{
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/* [0]:IBUSERR */
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rt_kprintf("IBUSERR ");
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}
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if(SCB_CFSR_BFSR & (1<<1))
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{
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/* [1]:PRECISERR */
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rt_kprintf("PRECISERR ");
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}
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if(SCB_CFSR_BFSR & (1<<2))
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{
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/* [2]:IMPRECISERR */
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rt_kprintf("IMPRECISERR ");
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}
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if(SCB_CFSR_BFSR & (1<<3))
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{
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/* [3]:UNSTKERR */
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rt_kprintf("UNSTKERR ");
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}
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if(SCB_CFSR_BFSR & (1<<4))
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{
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/* [4]:STKERR */
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rt_kprintf("STKERR ");
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}
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if(SCB_CFSR_BFSR & (1<<7))
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{
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rt_kprintf("SCB->BFAR:%08X\n", SCB_BFAR);
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}
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else
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{
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rt_kprintf("\n");
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}
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}
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static void mem_manage_fault_track(void)
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{
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rt_kprintf("mem manage fault:\n");
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rt_kprintf("SCB_CFSR_MFSR:0x%02X ", SCB_CFSR_MFSR);
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if(SCB_CFSR_MFSR & (1<<0))
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{
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/* [0]:IACCVIOL */
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rt_kprintf("IACCVIOL ");
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}
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||
|
|
|
||
|
|
if(SCB_CFSR_MFSR & (1<<1))
|
||
|
|
{
|
||
|
|
/* [1]:DACCVIOL */
|
||
|
|
rt_kprintf("DACCVIOL ");
|
||
|
|
}
|
||
|
|
|
||
|
|
if(SCB_CFSR_MFSR & (1<<3))
|
||
|
|
{
|
||
|
|
/* [3]:MUNSTKERR */
|
||
|
|
rt_kprintf("MUNSTKERR ");
|
||
|
|
}
|
||
|
|
|
||
|
|
if(SCB_CFSR_MFSR & (1<<4))
|
||
|
|
{
|
||
|
|
/* [4]:MSTKERR */
|
||
|
|
rt_kprintf("MSTKERR ");
|
||
|
|
}
|
||
|
|
|
||
|
|
if(SCB_CFSR_MFSR & (1<<7))
|
||
|
|
{
|
||
|
|
/* [7]:MMARVALID */
|
||
|
|
rt_kprintf("SCB->MMAR:%08X\n", SCB_MMAR);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
rt_kprintf("\n");
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void hard_fault_track(void)
|
||
|
|
{
|
||
|
|
if(SCB_HFSR & (1UL<<1))
|
||
|
|
{
|
||
|
|
/* [1]:VECTBL, Indicates hard fault is caused by failed vector fetch. */
|
||
|
|
rt_kprintf("failed vector fetch\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
if(SCB_HFSR & (1UL<<30))
|
||
|
|
{
|
||
|
|
/* [30]:FORCED, Indicates hard fault is taken because of bus fault,
|
||
|
|
memory management fault, or usage fault. */
|
||
|
|
if(SCB_CFSR_BFSR)
|
||
|
|
{
|
||
|
|
bus_fault_track();
|
||
|
|
}
|
||
|
|
|
||
|
|
if(SCB_CFSR_MFSR)
|
||
|
|
{
|
||
|
|
mem_manage_fault_track();
|
||
|
|
}
|
||
|
|
|
||
|
|
if(SCB_CFSR_UFSR)
|
||
|
|
{
|
||
|
|
usage_fault_track();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if(SCB_HFSR & (1UL<<31))
|
||
|
|
{
|
||
|
|
/* [31]:DEBUGEVT, Indicates hard fault is triggered by debug event. */
|
||
|
|
rt_kprintf("debug event\n");
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif /* RT_USING_FINSH */
|
||
|
|
|
||
|
|
struct exception_info
|
||
|
|
{
|
||
|
|
rt_uint32_t exc_return;
|
||
|
|
struct stack_frame stack_frame;
|
||
|
|
};
|
||
|
|
|
||
|
|
void rt_hw_hard_fault_exception(struct exception_info *exception_info)
|
||
|
|
{
|
||
|
|
#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS)
|
||
|
|
extern long list_thread(void);
|
||
|
|
#endif
|
||
|
|
struct exception_stack_frame *exception_stack = &exception_info->stack_frame.exception_stack_frame;
|
||
|
|
struct stack_frame *context = &exception_info->stack_frame;
|
||
|
|
|
||
|
|
if (rt_exception_hook != RT_NULL)
|
||
|
|
{
|
||
|
|
rt_err_t result;
|
||
|
|
|
||
|
|
result = rt_exception_hook(exception_stack);
|
||
|
|
if (result == RT_EOK) return;
|
||
|
|
}
|
||
|
|
|
||
|
|
rt_kprintf("psr: 0x%08x\n", context->exception_stack_frame.psr);
|
||
|
|
|
||
|
|
rt_kprintf("r00: 0x%08x\n", context->exception_stack_frame.r0);
|
||
|
|
rt_kprintf("r01: 0x%08x\n", context->exception_stack_frame.r1);
|
||
|
|
rt_kprintf("r02: 0x%08x\n", context->exception_stack_frame.r2);
|
||
|
|
rt_kprintf("r03: 0x%08x\n", context->exception_stack_frame.r3);
|
||
|
|
rt_kprintf("r04: 0x%08x\n", context->r4);
|
||
|
|
rt_kprintf("r05: 0x%08x\n", context->r5);
|
||
|
|
rt_kprintf("r06: 0x%08x\n", context->r6);
|
||
|
|
rt_kprintf("r07: 0x%08x\n", context->r7);
|
||
|
|
rt_kprintf("r08: 0x%08x\n", context->r8);
|
||
|
|
rt_kprintf("r09: 0x%08x\n", context->r9);
|
||
|
|
rt_kprintf("r10: 0x%08x\n", context->r10);
|
||
|
|
rt_kprintf("r11: 0x%08x\n", context->r11);
|
||
|
|
rt_kprintf("r12: 0x%08x\n", context->exception_stack_frame.r12);
|
||
|
|
rt_kprintf(" lr: 0x%08x\n", context->exception_stack_frame.lr);
|
||
|
|
rt_kprintf(" pc: 0x%08x\n", context->exception_stack_frame.pc);
|
||
|
|
|
||
|
|
if (exception_info->exc_return & (1 << 2))
|
||
|
|
{
|
||
|
|
rt_kprintf("hard fault on thread: %s\r\n\r\n", rt_thread_self()->parent.name);
|
||
|
|
|
||
|
|
#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS)
|
||
|
|
list_thread();
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
rt_kprintf("hard fault on handler\r\n\r\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
if ( (exception_info->exc_return & 0x10) == 0)
|
||
|
|
{
|
||
|
|
rt_kprintf("FPU active!\r\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef RT_USING_FINSH
|
||
|
|
hard_fault_track();
|
||
|
|
#endif /* RT_USING_FINSH */
|
||
|
|
|
||
|
|
while (1);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* shutdown CPU
|
||
|
|
*/
|
||
|
|
rt_weak void rt_hw_cpu_shutdown(void)
|
||
|
|
{
|
||
|
|
rt_kprintf("shutdown...\n");
|
||
|
|
|
||
|
|
RT_ASSERT(0);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* reset CPU
|
||
|
|
*/
|
||
|
|
rt_weak void rt_hw_cpu_reset(void)
|
||
|
|
{
|
||
|
|
SCB_AIRCR = SCB_RESET_VALUE;
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef RT_USING_CPU_FFS
|
||
|
|
/**
|
||
|
|
* This function finds the first bit set (beginning with the least significant bit)
|
||
|
|
* in value and return the index of that bit.
|
||
|
|
*
|
||
|
|
* Bits are numbered starting at 1 (the least significant bit). A return value of
|
||
|
|
* zero from any of these functions means that the argument was zero.
|
||
|
|
*
|
||
|
|
* @return return the index of the first bit set. If value is 0, then this function
|
||
|
|
* shall return 0.
|
||
|
|
*/
|
||
|
|
#if defined(__CC_ARM)
|
||
|
|
__asm int __rt_ffs(int value)
|
||
|
|
{
|
||
|
|
CMP r0, #0x00
|
||
|
|
BEQ exit
|
||
|
|
|
||
|
|
RBIT r0, r0
|
||
|
|
CLZ r0, r0
|
||
|
|
ADDS r0, r0, #0x01
|
||
|
|
|
||
|
|
exit
|
||
|
|
BX lr
|
||
|
|
}
|
||
|
|
#elif defined(__clang__)
|
||
|
|
int __rt_ffs(int value)
|
||
|
|
{
|
||
|
|
if (value == 0) return value;
|
||
|
|
|
||
|
|
__asm volatile(
|
||
|
|
"RBIT r0, r0 \n"
|
||
|
|
"CLZ r0, r0 \n"
|
||
|
|
"ADDS r0, r0, #0x01 \n"
|
||
|
|
|
||
|
|
: "=r"(value)
|
||
|
|
: "r"(value)
|
||
|
|
);
|
||
|
|
return value;
|
||
|
|
}
|
||
|
|
#elif defined(__IAR_SYSTEMS_ICC__)
|
||
|
|
int __rt_ffs(int value)
|
||
|
|
{
|
||
|
|
if (value == 0) return value;
|
||
|
|
|
||
|
|
asm("RBIT %0, %1" : "=r"(value) : "r"(value));
|
||
|
|
asm("CLZ %0, %1" : "=r"(value) : "r"(value));
|
||
|
|
asm("ADDS %0, %1, #0x01" : "=r"(value) : "r"(value));
|
||
|
|
|
||
|
|
return value;
|
||
|
|
}
|
||
|
|
#elif defined(__GNUC__)
|
||
|
|
int __rt_ffs(int value)
|
||
|
|
{
|
||
|
|
return __builtin_ffs(value);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif
|