140 lines
3.3 KiB
ArmAsm
140 lines
3.3 KiB
ArmAsm
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2015-04-06 zchong change to iar compiler from convert from cp15_gcc.S
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*/
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SECTION .text:CODE:NOROOT(2)
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ARM
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EXPORT rt_cpu_vector_set_base
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rt_cpu_vector_set_base:
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MCR p15, #0, r0, c12, c0, #0
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DSB
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BX lr
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EXPORT rt_cpu_vector_get_base
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rt_cpu_vector_get_base:
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MRC p15, #0, r0, c12, c0, #0
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BX lr
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EXPORT rt_cpu_get_sctlr
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rt_cpu_get_sctlr:
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MRC p15, #0, r0, c1, c0, #0
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BX lr
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EXPORT rt_cpu_dcache_enable
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rt_cpu_dcache_enable:
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MRC p15, #0, r0, c1, c0, #0
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ORR r0, r0, #0x00000004
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MCR p15, #0, r0, c1, c0, #0
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BX lr
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EXPORT rt_cpu_icache_enable
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rt_cpu_icache_enable:
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MRC p15, #0, r0, c1, c0, #0
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ORR r0, r0, #0x00001000
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MCR p15, #0, r0, c1, c0, #0
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BX lr
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;_FLD_MAX_WAY DEFINE 0x3ff
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;_FLD_MAX_IDX DEFINE 0x7ff
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EXPORT rt_cpu_dcache_clean_flush
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rt_cpu_dcache_clean_flush:
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PUSH {r4-r11}
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DMB
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MRC p15, #1, r0, c0, c0, #1 ; read clid register
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ANDS r3, r0, #0x7000000 ; get level of coherency
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MOV r3, r3, lsr #23
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BEQ finished
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MOV r10, #0
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loop1:
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ADD r2, r10, r10, lsr #1
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MOV r1, r0, lsr r2
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AND r1, r1, #7
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CMP r1, #2
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BLT skip
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MCR p15, #2, r10, c0, c0, #0
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ISB
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MRC p15, #1, r1, c0, c0, #0
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AND r2, r1, #7
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ADD r2, r2, #4
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;LDR r4, _FLD_MAX_WAY
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LDR r4, =0x3FF
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ANDS r4, r4, r1, lsr #3
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CLZ r5, r4
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;LDR r7, _FLD_MAX_IDX
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LDR r7, =0x7FF
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ANDS r7, r7, r1, lsr #13
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loop2:
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MOV r9, r4
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loop3:
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ORR r11, r10, r9, lsl r5
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ORR r11, r11, r7, lsl r2
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MCR p15, #0, r11, c7, c14, #2
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SUBS r9, r9, #1
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BGE loop3
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SUBS r7, r7, #1
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BGE loop2
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skip:
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ADD r10, r10, #2
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CMP r3, r10
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BGT loop1
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finished:
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DSB
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ISB
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POP {r4-r11}
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BX lr
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EXPORT rt_cpu_dcache_disable
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rt_cpu_dcache_disable:
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PUSH {r4-r11, lr}
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MRC p15, #0, r0, c1, c0, #0
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BIC r0, r0, #0x00000004
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MCR p15, #0, r0, c1, c0, #0
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BL rt_cpu_dcache_clean_flush
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POP {r4-r11, lr}
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BX lr
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EXPORT rt_cpu_icache_disable
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rt_cpu_icache_disable:
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MRC p15, #0, r0, c1, c0, #0
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BIC r0, r0, #0x00001000
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MCR p15, #0, r0, c1, c0, #0
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BX lr
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EXPORT rt_cpu_mmu_disable
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rt_cpu_mmu_disable:
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MCR p15, #0, r0, c8, c7, #0 ; invalidate tlb
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MRC p15, #0, r0, c1, c0, #0
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BIC r0, r0, #1
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MCR p15, #0, r0, c1, c0, #0 ; clear mmu bit
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DSB
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BX lr
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EXPORT rt_cpu_mmu_enable
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rt_cpu_mmu_enable:
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MRC p15, #0, r0, c1, c0, #0
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ORR r0, r0, #0x001
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MCR p15, #0, r0, c1, c0, #0 ; set mmu enable bit
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DSB
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BX lr
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EXPORT rt_cpu_tlb_set
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rt_cpu_tlb_set:
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MCR p15, #0, r0, c2, c0, #0
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DMB
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BX lr
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END
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