732 lines
17 KiB
C
732 lines
17 KiB
C
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-12-10 zylx first version
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* 2020-06-16 thread-liu Porting for stm32mp1
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* 2020-08-25 linyongkang Fix the timer clock frequency doubling problem
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* 2020-10-14 Dozingfiretruck Porting for stm32wbxx
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* 2020-11-18 leizhixiong add STM32H7 series support
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*/
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#include <rtdevice.h>
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#include "drv_config.h"
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//#define DRV_DEBUG
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#define LOG_TAG "drv.tim"
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#include <drv_log.h>
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/* APBx timer clocks frequency doubler state related to APB1CLKDivider value */
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void stm32_tim_pclkx_doubler_get(rt_uint32_t *pclk1_doubler, rt_uint32_t *pclk2_doubler)
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{
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rt_uint32_t flatency = 0;
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RT_ASSERT(pclk1_doubler != RT_NULL);
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RT_ASSERT(pclk1_doubler != RT_NULL);
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HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &flatency);
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*pclk1_doubler = 1;
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*pclk2_doubler = 1;
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#if defined(SOC_SERIES_STM32MP1)
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if (RCC_ClkInitStruct.APB1_Div != RCC_APB1_DIV1)
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{
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*pclk1_doubler = 2;
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}
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if (RCC_ClkInitStruct.APB2_Div != RCC_APB2_DIV1)
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{
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*pclk2_doubler = 2;
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}
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#else
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if (RCC_ClkInitStruct.APB1CLKDivider != RCC_HCLK_DIV1)
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{
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*pclk1_doubler = 2;
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}
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#if !(defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0))
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if (RCC_ClkInitStruct.APB2CLKDivider != RCC_HCLK_DIV1)
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{
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*pclk2_doubler = 2;
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}
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#endif /* !(defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)) */
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#endif /* defined(SOC_SERIES_STM32MP1) */
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}
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void stm32_tim_enable_clock(TIM_HandleTypeDef* htim_base)
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{
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RT_ASSERT(htim_base != RT_NULL);
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if(RT_FALSE);
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#ifdef TIM1
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else if(htim_base->Instance==TIM1)
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{
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__HAL_RCC_TIM1_CLK_ENABLE();
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}
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#endif /* TIM1 */
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#ifdef TIM2
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else if(htim_base->Instance==TIM2)
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{
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__HAL_RCC_TIM2_CLK_ENABLE();
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}
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#endif /* TIM2 */
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#ifdef TIM3
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else if(htim_base->Instance==TIM3)
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{
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__HAL_RCC_TIM3_CLK_ENABLE();
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}
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#endif /* TIM3 */
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#ifdef TIM4
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else if(htim_base->Instance==TIM4)
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{
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__HAL_RCC_TIM4_CLK_ENABLE();
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}
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#endif /* TIM4 */
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#ifdef TIM5
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else if(htim_base->Instance==TIM5)
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{
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__HAL_RCC_TIM5_CLK_ENABLE();
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}
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#endif /* TIM5 */
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#ifdef TIM6
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else if(htim_base->Instance==TIM6)
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{
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__HAL_RCC_TIM6_CLK_ENABLE();
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}
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#endif /* TIM6 */
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#ifdef TIM7
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else if(htim_base->Instance==TIM7)
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{
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__HAL_RCC_TIM7_CLK_ENABLE();
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}
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#endif /* TIM7 */
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#ifdef TIM8
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else if(htim_base->Instance==TIM8)
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{
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__HAL_RCC_TIM8_CLK_ENABLE();
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}
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#endif /* TIM8 */
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#ifdef TIM9
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else if(htim_base->Instance==TIM9)
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{
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__HAL_RCC_TIM9_CLK_ENABLE();
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}
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#endif /* TIM9 */
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#ifdef TIM10
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else if(htim_base->Instance==TIM10)
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{
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__HAL_RCC_TIM10_CLK_ENABLE();
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}
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#endif /* TIM10 */
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#ifdef TIM11
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else if(htim_base->Instance==TIM11)
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{
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__HAL_RCC_TIM11_CLK_ENABLE();
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}
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#endif /* TIM11 */
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#ifdef TIM12
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else if(htim_base->Instance==TIM12)
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{
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__HAL_RCC_TIM12_CLK_ENABLE();
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}
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#endif /* TIM12 */
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#ifdef TIM13
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else if(htim_base->Instance==TIM13)
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{
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__HAL_RCC_TIM13_CLK_ENABLE();
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}
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#endif /* TIM13 */
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#ifdef TIM14
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else if(htim_base->Instance==TIM14)
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{
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__HAL_RCC_TIM14_CLK_ENABLE();
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}
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#endif /* TIM14 */
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#ifdef TIM15
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else if(htim_base->Instance==TIM15)
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{
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__HAL_RCC_TIM15_CLK_ENABLE();
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}
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#endif /* TIM15 */
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#ifdef TIM16
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else if(htim_base->Instance==TIM16)
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{
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__HAL_RCC_TIM16_CLK_ENABLE();
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}
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#endif /* TIM16 */
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#ifdef TIM17
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else if(htim_base->Instance==TIM17)
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{
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__HAL_RCC_TIM17_CLK_ENABLE();
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}
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#endif /* TIM17 */
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#ifdef TIM18
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else if(htim_base->Instance==TIM18)
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{
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__HAL_RCC_TIM18_CLK_ENABLE();
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}
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#endif /* TIM18 */
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#ifdef TIM19
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else if(htim_base->Instance==TIM19)
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{
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__HAL_RCC_TIM19_CLK_ENABLE();
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}
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#endif /* TIM19 */
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else
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{
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RT_ASSERT(RT_TRUE);
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}
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}
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#ifdef BSP_USING_TIM
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enum
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{
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#ifdef BSP_USING_TIM1
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TIM1_INDEX,
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#endif
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#ifdef BSP_USING_TIM2
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TIM2_INDEX,
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#endif
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#ifdef BSP_USING_TIM3
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TIM3_INDEX,
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#endif
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#ifdef BSP_USING_TIM4
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TIM4_INDEX,
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#endif
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#ifdef BSP_USING_TIM5
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TIM5_INDEX,
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#endif
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#ifdef BSP_USING_TIM6
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TIM6_INDEX,
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#endif
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#ifdef BSP_USING_TIM7
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TIM7_INDEX,
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#endif
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#ifdef BSP_USING_TIM8
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TIM8_INDEX,
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#endif
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#ifdef BSP_USING_TIM9
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TIM9_INDEX,
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#endif
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#ifdef BSP_USING_TIM10
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TIM10_INDEX,
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#endif
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#ifdef BSP_USING_TIM11
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TIM11_INDEX,
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#endif
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#ifdef BSP_USING_TIM12
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TIM12_INDEX,
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#endif
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#ifdef BSP_USING_TIM13
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TIM13_INDEX,
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#endif
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#ifdef BSP_USING_TIM14
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TIM14_INDEX,
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#endif
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#ifdef BSP_USING_TIM15
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TIM15_INDEX,
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#endif
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#ifdef BSP_USING_TIM16
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TIM16_INDEX,
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#endif
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#ifdef BSP_USING_TIM17
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TIM17_INDEX,
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#endif
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};
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struct stm32_hwtimer
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{
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rt_hwtimer_t time_device;
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TIM_HandleTypeDef tim_handle;
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IRQn_Type tim_irqn;
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char *name;
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};
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static struct stm32_hwtimer stm32_hwtimer_obj[] =
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{
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#ifdef BSP_USING_TIM1
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TIM1_CONFIG,
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#endif
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#ifdef BSP_USING_TIM2
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TIM2_CONFIG,
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#endif
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#ifdef BSP_USING_TIM3
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TIM3_CONFIG,
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#endif
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#ifdef BSP_USING_TIM4
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TIM4_CONFIG,
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#endif
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#ifdef BSP_USING_TIM5
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TIM5_CONFIG,
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#endif
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#ifdef BSP_USING_TIM6
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TIM6_CONFIG,
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#endif
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#ifdef BSP_USING_TIM7
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TIM7_CONFIG,
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#endif
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#ifdef BSP_USING_TIM8
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TIM8_CONFIG,
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#endif
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#ifdef BSP_USING_TIM9
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TIM9_CONFIG,
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#endif
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#ifdef BSP_USING_TIM10
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TIM10_CONFIG,
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#endif
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#ifdef BSP_USING_TIM11
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TIM11_CONFIG,
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#endif
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#ifdef BSP_USING_TIM12
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TIM12_CONFIG,
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#endif
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#ifdef BSP_USING_TIM13
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TIM13_CONFIG,
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#endif
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#ifdef BSP_USING_TIM14
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TIM14_CONFIG,
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#endif
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#ifdef BSP_USING_TIM15
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TIM15_CONFIG,
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#endif
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#ifdef BSP_USING_TIM16
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TIM16_CONFIG,
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#endif
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#ifdef BSP_USING_TIM17
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TIM17_CONFIG,
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#endif
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};
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static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
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{
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uint32_t prescaler_value = 0;
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uint32_t pclk1_doubler, pclk2_doubler;
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TIM_HandleTypeDef *tim = RT_NULL;
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struct stm32_hwtimer *tim_device = RT_NULL;
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RT_ASSERT(timer != RT_NULL);
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if (state)
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{
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tim = (TIM_HandleTypeDef *)timer->parent.user_data;
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tim_device = (struct stm32_hwtimer *)timer;
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stm32_tim_pclkx_doubler_get(&pclk1_doubler, &pclk2_doubler);
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/* time init */
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/* Some series may only have APBPERIPH_BASE, don't have HAL_RCC_GetPCLK2Freq */
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#if defined(APBPERIPH_BASE)
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prescaler_value = (uint32_t)(HAL_RCC_GetPCLK1Freq() * pclk1_doubler / 10000) - 1;
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#elif defined(APB1PERIPH_BASE) || defined(APB2PERIPH_BASE)
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if ((rt_uint32_t)tim->Instance >= APB2PERIPH_BASE)
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{
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prescaler_value = (uint32_t)(HAL_RCC_GetPCLK2Freq() * pclk2_doubler / 10000) - 1;
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}
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else
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{
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prescaler_value = (uint32_t)(HAL_RCC_GetPCLK1Freq() * pclk1_doubler / 10000) - 1;
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}
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#endif
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tim->Init.Period = 10000 - 1;
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tim->Init.Prescaler = prescaler_value;
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tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
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if (timer->info->cntmode == HWTIMER_CNTMODE_UP)
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{
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tim->Init.CounterMode = TIM_COUNTERMODE_UP;
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}
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else
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{
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tim->Init.CounterMode = TIM_COUNTERMODE_DOWN;
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}
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tim->Init.RepetitionCounter = 0;
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#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)
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tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
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#endif
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if (HAL_TIM_Base_Init(tim) != HAL_OK)
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{
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LOG_E("%s init failed", tim_device->name);
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return;
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}
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stm32_tim_enable_clock(tim);
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HAL_NVIC_SetPriority(tim_device->tim_irqn, 3, 0); /* set the TIMx priority */
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HAL_NVIC_EnableIRQ(tim_device->tim_irqn); /* enable the TIMx global Interrupt */
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__HAL_TIM_CLEAR_FLAG(tim, TIM_FLAG_UPDATE); /* clear update flag */
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__HAL_TIM_URS_ENABLE(tim); /* enable update request source */
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LOG_D("%s init success", tim_device->name);
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}
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}
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static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
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{
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rt_err_t result = RT_EOK;
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TIM_HandleTypeDef *tim = RT_NULL;
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RT_ASSERT(timer != RT_NULL);
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tim = (TIM_HandleTypeDef *)timer->parent.user_data;
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/* set tim cnt */
|
||
|
|
__HAL_TIM_SET_COUNTER(tim, 0);
|
||
|
|
/* set tim arr */
|
||
|
|
__HAL_TIM_SET_AUTORELOAD(tim, t - 1);
|
||
|
|
|
||
|
|
if (opmode == HWTIMER_MODE_ONESHOT)
|
||
|
|
{
|
||
|
|
/* set timer to single mode */
|
||
|
|
tim->Instance->CR1 |= TIM_OPMODE_SINGLE;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
tim->Instance->CR1 &= (~TIM_OPMODE_SINGLE);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* start timer */
|
||
|
|
if (HAL_TIM_Base_Start_IT(tim) != HAL_OK)
|
||
|
|
{
|
||
|
|
LOG_E("TIM start failed");
|
||
|
|
result = -RT_ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void timer_stop(rt_hwtimer_t *timer)
|
||
|
|
{
|
||
|
|
TIM_HandleTypeDef *tim = RT_NULL;
|
||
|
|
|
||
|
|
RT_ASSERT(timer != RT_NULL);
|
||
|
|
|
||
|
|
tim = (TIM_HandleTypeDef *)timer->parent.user_data;
|
||
|
|
|
||
|
|
/* stop timer */
|
||
|
|
HAL_TIM_Base_Stop_IT(tim);
|
||
|
|
|
||
|
|
/* set tim cnt */
|
||
|
|
__HAL_TIM_SET_COUNTER(tim, 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
|
||
|
|
{
|
||
|
|
TIM_HandleTypeDef *tim = RT_NULL;
|
||
|
|
rt_err_t result = -RT_ERROR;
|
||
|
|
uint32_t pclk1_doubler, pclk2_doubler;
|
||
|
|
|
||
|
|
RT_ASSERT(timer != RT_NULL);
|
||
|
|
RT_ASSERT(arg != RT_NULL);
|
||
|
|
|
||
|
|
tim = (TIM_HandleTypeDef *)timer->parent.user_data;
|
||
|
|
|
||
|
|
switch (cmd)
|
||
|
|
{
|
||
|
|
case HWTIMER_CTRL_FREQ_SET:
|
||
|
|
{
|
||
|
|
rt_uint32_t freq;
|
||
|
|
rt_uint16_t val;
|
||
|
|
|
||
|
|
/* set timer frequence */
|
||
|
|
freq = *((rt_uint32_t *)arg);
|
||
|
|
|
||
|
|
stm32_tim_pclkx_doubler_get(&pclk1_doubler, &pclk2_doubler);
|
||
|
|
|
||
|
|
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||
|
|
if (tim->Instance == TIM1 || tim->Instance == TIM8 || tim->Instance == TIM9 || tim->Instance == TIM10 || tim->Instance == TIM11)
|
||
|
|
#elif defined(SOC_SERIES_STM32L4)
|
||
|
|
if (tim->Instance == TIM15 || tim->Instance == TIM16 || tim->Instance == TIM17)
|
||
|
|
#elif defined(SOC_SERIES_STM32WB)
|
||
|
|
if (tim->Instance == TIM16 || tim->Instance == TIM17)
|
||
|
|
#elif defined(SOC_SERIES_STM32MP1)
|
||
|
|
if(tim->Instance == TIM14 || tim->Instance == TIM16 || tim->Instance == TIM17)
|
||
|
|
#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7)
|
||
|
|
if (0)
|
||
|
|
#else
|
||
|
|
#error "This driver has not supported this series yet!"
|
||
|
|
#endif
|
||
|
|
{
|
||
|
|
#if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
|
||
|
|
val = HAL_RCC_GetPCLK2Freq() * pclk2_doubler / freq;
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
val = HAL_RCC_GetPCLK1Freq() * pclk1_doubler / freq;
|
||
|
|
}
|
||
|
|
__HAL_TIM_SET_PRESCALER(tim, val - 1);
|
||
|
|
|
||
|
|
/* Update frequency value */
|
||
|
|
tim->Instance->EGR |= TIM_EVENTSOURCE_UPDATE;
|
||
|
|
|
||
|
|
result = RT_EOK;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
{
|
||
|
|
result = -RT_EINVAL;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer)
|
||
|
|
{
|
||
|
|
TIM_HandleTypeDef *tim = RT_NULL;
|
||
|
|
|
||
|
|
RT_ASSERT(timer != RT_NULL);
|
||
|
|
|
||
|
|
tim = (TIM_HandleTypeDef *)timer->parent.user_data;
|
||
|
|
|
||
|
|
return tim->Instance->CNT;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG;
|
||
|
|
|
||
|
|
static const struct rt_hwtimer_ops _ops =
|
||
|
|
{
|
||
|
|
.init = timer_init,
|
||
|
|
.start = timer_start,
|
||
|
|
.stop = timer_stop,
|
||
|
|
.count_get = timer_counter_get,
|
||
|
|
.control = timer_ctrl,
|
||
|
|
};
|
||
|
|
|
||
|
|
#ifdef BSP_USING_TIM2
|
||
|
|
void TIM2_IRQHandler(void)
|
||
|
|
{
|
||
|
|
/* enter interrupt */
|
||
|
|
rt_interrupt_enter();
|
||
|
|
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM2_INDEX].tim_handle);
|
||
|
|
/* leave interrupt */
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TIM3
|
||
|
|
void TIM3_IRQHandler(void)
|
||
|
|
{
|
||
|
|
/* enter interrupt */
|
||
|
|
rt_interrupt_enter();
|
||
|
|
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM3_INDEX].tim_handle);
|
||
|
|
/* leave interrupt */
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TIM4
|
||
|
|
void TIM4_IRQHandler(void)
|
||
|
|
{
|
||
|
|
/* enter interrupt */
|
||
|
|
rt_interrupt_enter();
|
||
|
|
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM4_INDEX].tim_handle);
|
||
|
|
/* leave interrupt */
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TIM5
|
||
|
|
void TIM5_IRQHandler(void)
|
||
|
|
{
|
||
|
|
/* enter interrupt */
|
||
|
|
rt_interrupt_enter();
|
||
|
|
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM5_INDEX].tim_handle);
|
||
|
|
/* leave interrupt */
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TIM7
|
||
|
|
void TIM7_IRQHandler(void)
|
||
|
|
{
|
||
|
|
/* enter interrupt */
|
||
|
|
rt_interrupt_enter();
|
||
|
|
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM7_INDEX].tim_handle);
|
||
|
|
/* leave interrupt */
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TIM11
|
||
|
|
void TIM1_TRG_COM_TIM11_IRQHandler(void)
|
||
|
|
{
|
||
|
|
/* enter interrupt */
|
||
|
|
rt_interrupt_enter();
|
||
|
|
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM11_INDEX].tim_handle);
|
||
|
|
/* leave interrupt */
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TIM13
|
||
|
|
void TIM8_UP_TIM13_IRQHandler(void)
|
||
|
|
{
|
||
|
|
/* enter interrupt */
|
||
|
|
rt_interrupt_enter();
|
||
|
|
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM13_INDEX].tim_handle);
|
||
|
|
/* leave interrupt */
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TIM14
|
||
|
|
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||
|
|
void TIM8_TRG_COM_TIM14_IRQHandler(void)
|
||
|
|
#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
|
||
|
|
void TIM14_IRQHandler(void)
|
||
|
|
#endif
|
||
|
|
{
|
||
|
|
/* enter interrupt */
|
||
|
|
rt_interrupt_enter();
|
||
|
|
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM14_INDEX].tim_handle);
|
||
|
|
/* leave interrupt */
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TIM15
|
||
|
|
void TIM1_BRK_TIM15_IRQHandler(void)
|
||
|
|
{
|
||
|
|
/* enter interrupt */
|
||
|
|
rt_interrupt_enter();
|
||
|
|
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM15_INDEX].tim_handle);
|
||
|
|
/* leave interrupt */
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TIM16
|
||
|
|
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB)
|
||
|
|
void TIM1_UP_TIM16_IRQHandler(void)
|
||
|
|
#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
|
||
|
|
void TIM16_IRQHandler(void)
|
||
|
|
#endif
|
||
|
|
{
|
||
|
|
/* enter interrupt */
|
||
|
|
rt_interrupt_enter();
|
||
|
|
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM16_INDEX].tim_handle);
|
||
|
|
/* leave interrupt */
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TIM17
|
||
|
|
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB)
|
||
|
|
void TIM1_TRG_COM_TIM17_IRQHandler(void)
|
||
|
|
#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
|
||
|
|
void TIM17_IRQHandler(void)
|
||
|
|
#endif
|
||
|
|
{
|
||
|
|
/* enter interrupt */
|
||
|
|
rt_interrupt_enter();
|
||
|
|
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM17_INDEX].tim_handle);
|
||
|
|
/* leave interrupt */
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
|
||
|
|
{
|
||
|
|
#ifdef BSP_USING_TIM2
|
||
|
|
if (htim->Instance == TIM2)
|
||
|
|
{
|
||
|
|
rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM2_INDEX].time_device);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TIM3
|
||
|
|
if (htim->Instance == TIM3)
|
||
|
|
{
|
||
|
|
rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM3_INDEX].time_device);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TIM4
|
||
|
|
if (htim->Instance == TIM4)
|
||
|
|
{
|
||
|
|
rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM4_INDEX].time_device);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TIM5
|
||
|
|
if (htim->Instance == TIM5)
|
||
|
|
{
|
||
|
|
rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM5_INDEX].time_device);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TIM7
|
||
|
|
if (htim->Instance == TIM7)
|
||
|
|
{
|
||
|
|
rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM7_INDEX].time_device);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TIM11
|
||
|
|
if (htim->Instance == TIM11)
|
||
|
|
{
|
||
|
|
rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM11_INDEX].time_device);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TIM13
|
||
|
|
if (htim->Instance == TIM13)
|
||
|
|
{
|
||
|
|
rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM13_INDEX].time_device);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TIM14
|
||
|
|
if (htim->Instance == TIM14)
|
||
|
|
{
|
||
|
|
rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM14_INDEX].time_device);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TIM15
|
||
|
|
if (htim->Instance == TIM15)
|
||
|
|
{
|
||
|
|
rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM15_INDEX].time_device);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TIM16
|
||
|
|
if (htim->Instance == TIM16)
|
||
|
|
{
|
||
|
|
rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM16_INDEX].time_device);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_TIM17
|
||
|
|
if (htim->Instance == TIM17)
|
||
|
|
{
|
||
|
|
rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM17_INDEX].time_device);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
static int stm32_hwtimer_init(void)
|
||
|
|
{
|
||
|
|
int i = 0;
|
||
|
|
int result = RT_EOK;
|
||
|
|
|
||
|
|
for (i = 0; i < sizeof(stm32_hwtimer_obj) / sizeof(stm32_hwtimer_obj[0]); i++)
|
||
|
|
{
|
||
|
|
stm32_hwtimer_obj[i].time_device.info = &_info;
|
||
|
|
stm32_hwtimer_obj[i].time_device.ops = &_ops;
|
||
|
|
if (rt_device_hwtimer_register(&stm32_hwtimer_obj[i].time_device,
|
||
|
|
stm32_hwtimer_obj[i].name, &stm32_hwtimer_obj[i].tim_handle) == RT_EOK)
|
||
|
|
{
|
||
|
|
LOG_D("%s register success", stm32_hwtimer_obj[i].name);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
LOG_E("%s register failed", stm32_hwtimer_obj[i].name);
|
||
|
|
result = -RT_ERROR;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
INIT_BOARD_EXPORT(stm32_hwtimer_init);
|
||
|
|
|
||
|
|
#endif /* BSP_USING_TIM */
|