130 lines
5.4 KiB
C
130 lines
5.4 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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* @file xil_mmu.h
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*
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* @addtogroup r5_mpu_apis Cortex R5 Processor MPU specific APIs
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*
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* MPU functions provides access to MPU operations such as enable MPU, disable
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* MPU and set attribute for section of memory.
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* Boot code invokes Init_MPU function to configure the MPU. A total of 10 MPU
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* regions are allocated with another 6 being free for users. Overview of the
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* memory attributes for different MPU regions is as given below,
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*
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*| | Memory Range | Attributes of MPURegion |
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*|-----------------------|-------------------------|-----------------------------|
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*| DDR | 0x00000000 - 0x7FFFFFFF | Normal write-back Cacheable |
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*| PL | 0x80000000 - 0xBFFFFFFF | Strongly Ordered |
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*| QSPI | 0xC0000000 - 0xDFFFFFFF | Device Memory |
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*| PCIe | 0xE0000000 - 0xEFFFFFFF | Device Memory |
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*| STM_CORESIGHT | 0xF8000000 - 0xF8FFFFFF | Device Memory |
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*| RPU_R5_GIC | 0xF9000000 - 0xF90FFFFF | Device memory |
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*| FPS | 0xFD000000 - 0xFDFFFFFF | Device Memory |
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*| LPS | 0xFE000000 - 0xFFFFFFFF | Device Memory |
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*| OCM | 0xFFFC0000 - 0xFFFFFFFF | Normal write-back Cacheable |
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*
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*
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* @note
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* For a system where DDR is less than 2GB, region after DDR and before PL is
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* marked as undefined in translation table. Memory range 0xFE000000-0xFEFFFFFF is
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* allocated for upper LPS slaves, where as memory region 0xFF000000-0xFFFFFFFF is
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* allocated for lower LPS slaves.
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*
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* @{
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- ---------------------------------------------------
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* 5.00 pkp 02/10/14 Initial version
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* 6.4 asa 08/16/17 Added many APIs for MPU access to make MPU usage
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* user-friendly. The APIs added are: Xil_UpdateMPUConfig,
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* Xil_GetMPUConfig, Xil_GetNumOfFreeRegions,
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* Xil_GetNextMPURegion, Xil_DisableMPURegionByRegNum,
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* Xil_GetMPUFreeRegMask, Xil_SetMPURegionByRegNum, and
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* Xil_InitializeExistingMPURegConfig.
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* Added a new array of structure of type XMpuConfig to
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* represent the MPU configuration table.
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* </pre>
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*
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*
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*
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******************************************************************************/
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#ifndef XIL_MPU_H
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#define XIL_MPU_H
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#include "xil_types.h"
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/***************************** Include Files *********************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define MPU_REG_DISABLED 0U
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#define MPU_REG_ENABLED 1U
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#define MAX_POSSIBLE_MPU_REGS 16U
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/**************************** Type Definitions *******************************/
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struct XMpuConfig{
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u32 RegionStatus; /* Enabled or disabled */
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INTPTR BaseAddress;/* MPU region base address */
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u64 Size; /* MPU region size address */
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u32 Attribute; /* MPU region size attribute */
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};
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typedef struct XMpuConfig XMpu_Config[MAX_POSSIBLE_MPU_REGS];
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extern XMpu_Config Mpu_Config;
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/************************** Constant Definitions *****************************/
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/************************** Variable Definitions *****************************/
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/************************** Function Prototypes ******************************/
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void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
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void Xil_EnableMPU(void);
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void Xil_DisableMPU(void);
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u32 Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib);
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u32 Xil_UpdateMPUConfig(u32 reg_num, INTPTR address, u32 size, u32 attrib);
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void Xil_GetMPUConfig (XMpu_Config mpuconfig);
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u32 Xil_GetNumOfFreeRegions (void);
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u32 Xil_GetNextMPURegion(void);
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u32 Xil_DisableMPURegionByRegNum (u32 reg_num);
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u16 Xil_GetMPUFreeRegMask (void);
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u32 Xil_SetMPURegionByRegNum (u32 reg_num, INTPTR addr, u64 size, u32 attrib);
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void* Xil_MemMap(UINTPTR Physaddr, size_t size, u32 flags);
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* XIL_MPU_H */
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/**
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* @} End of "addtogroup r5_mpu_apis".
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*/
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