681 lines
15 KiB
ArmAsm
681 lines
15 KiB
ArmAsm
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2013-07-05 Bernard the first version
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* 2018-11-22 Jesven in the interrupt context, use rt_scheduler_do_irq_switch checks
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* and switches to a new thread
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*/
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#include "rtconfig.h"
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.equ Mode_USR, 0x10
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.equ Mode_FIQ, 0x11
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.equ Mode_IRQ, 0x12
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.equ Mode_SVC, 0x13
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.equ Mode_ABT, 0x17
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.equ Mode_UND, 0x1B
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.equ Mode_SYS, 0x1F
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.equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */
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.equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */
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#ifdef RT_USING_SMART
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.data
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.align 14
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init_mtbl:
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.space 16*1024
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#endif
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.text
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/* reset entry */
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.globl _reset
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_reset:
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#ifdef ARCH_ARMV8
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/* Check for HYP mode */
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mrs r0, cpsr_all
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and r0, r0, #0x1F
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mov r8, #0x1A
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cmp r0, r8
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beq overHyped
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b continue
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overHyped: /* Get out of HYP mode */
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adr r1, continue
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msr ELR_hyp, r1
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mrs r1, cpsr_all
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and r1, r1, #0x1f /* CPSR_MODE_MASK */
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orr r1, r1, #0x13 /* CPSR_MODE_SUPERVISOR */
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msr SPSR_hyp, r1
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eret
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continue:
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#endif
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#ifdef SOC_BCM283x
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/* Suspend the other cpu cores */
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mrc p15, 0, r0, c0, c0, 5
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ands r0, #3
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bne _halt
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/* Disable IRQ & FIQ */
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cpsid if
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/* Check for HYP mode */
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mrs r0, cpsr_all
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and r0, r0, #0x1F
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mov r8, #0x1A
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cmp r0, r8
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beq overHyped
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b continue
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overHyped: /* Get out of HYP mode */
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adr r1, continue
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msr ELR_hyp, r1
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mrs r1, cpsr_all
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and r1, r1, #0x1f /* CPSR_MODE_MASK */
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orr r1, r1, #0x13 /* CPSR_MODE_SUPERVISOR */
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msr SPSR_hyp, r1
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eret
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continue:
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/* set the cpu to SVC32 mode and disable interrupt */
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mrs r0, cpsr
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bic r0, r0, #0x1f
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orr r0, r0, #0x13
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msr cpsr_c, r0
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#endif
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/* invalid tlb before enable mmu */
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mrc p15, 0, r0, c1, c0, 0
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bic r0, #1
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mcr p15, 0, r0, c1, c0, 0
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dsb
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isb
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mov r0, #0
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mcr p15, 0, r0, c8, c7, 0
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mcr p15, 0, r0, c7, c5, 0 /* iciallu */
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mcr p15, 0, r0, c7, c5, 6 /* bpiall */
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dsb
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isb
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#ifdef RT_USING_SMART
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/* load r5 with PV_OFFSET */
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ldr r7, =_reset
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adr r5, _reset
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sub r5, r5, r7
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mov r7, #0x100000
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sub r7, #1
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mvn r8, r7
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ldr r9, =KERNEL_VADDR_START
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ldr r6, =__bss_end
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add r6, r7
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and r6, r8 /* r6 end vaddr align up to 1M */
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sub r6, r9 /* r6 is size */
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ldr sp, =svc_stack_n_limit
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add sp, r5 /* use paddr */
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ldr r0, =init_mtbl
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add r0, r5
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mov r1, r6
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mov r2, r5
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bl init_mm_setup
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ldr lr, =after_enable_mmu
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ldr r0, =init_mtbl
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add r0, r5
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b enable_mmu
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after_enable_mmu:
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#endif
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#ifndef SOC_BCM283x
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/* set the cpu to SVC32 mode and disable interrupt */
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cps #Mode_SVC
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#endif
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#ifdef RT_USING_FPU
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mov r4, #0xfffffff
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mcr p15, 0, r4, c1, c0, 2
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#endif
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/* disable the data alignment check */
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mrc p15, 0, r1, c1, c0, 0
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bic r1, #(1<<1) /* Disable Alignment fault checking */
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#ifndef RT_USING_SMART
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bic r1, #(1<<0) /* Disable MMU */
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bic r1, #(1<<2) /* Disable data cache */
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bic r1, #(1<<11) /* Disable program flow prediction */
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bic r1, #(1<<12) /* Disable instruction cache */
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bic r1, #(3<<19) /* bit[20:19] must be zero */
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#endif /* RT_USING_SMART */
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mcr p15, 0, r1, c1, c0, 0
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/* enable I cache + branch prediction */
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #(1<<12)
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orr r0, r0, #(1<<11)
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mcr p15, 0, r0, c1, c0, 0
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/* setup stack */
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bl stack_setup
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/* clear .bss */
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mov r0,#0 /* get a zero */
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ldr r1,=__bss_start /* bss start */
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ldr r2,=__bss_end /* bss end */
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bss_loop:
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cmp r1,r2 /* check if data to clear */
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strlo r0,[r1],#4 /* clear 4 bytes */
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blo bss_loop /* loop until done */
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mov r0, r5
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bl rt_kmem_pvoff_set
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#ifdef RT_USING_SMP
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mrc p15, 0, r1, c1, c0, 1
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mov r0, #(1<<6)
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orr r1, r0
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mcr p15, 0, r1, c1, c0, 1 /* enable smp */
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#endif
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/**
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* void rt_hw_init_mmu_table(struct mem_desc *mdesc, rt_uint32_t size)
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* initialize the mmu table and enable mmu
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*/
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ldr r0, =platform_mem_desc
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ldr r1, =platform_mem_desc_size
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ldr r1, [r1]
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bl rt_hw_init_mmu_table
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#ifdef RT_USING_SMART
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ldr r0, =MMUTable /* vaddr */
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add r0, r5 /* to paddr */
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bl rt_hw_mmu_switch
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#else
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bl rt_hw_mmu_init
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#endif
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/* start RT-Thread Kernel */
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ldr pc, _rtthread_startup
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_rtthread_startup:
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.word rtthread_startup
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stack_setup:
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#ifdef RT_USING_SMP
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/* cpu id */
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mrc p15, 0, r0, c0, c0, 5
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and r0, r0, #0xf
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add r0, r0, #1
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#else
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mov r0, #1
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#endif
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cps #Mode_UND
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ldr r1, =und_stack_n
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add sp, r1, r0, asl #12
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cps #Mode_IRQ
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ldr r1, =irq_stack_n
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add sp, r1, r0, asl #12
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cps #Mode_FIQ
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ldr r1, =irq_stack_n
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add sp, r1, r0, asl #12
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cps #Mode_ABT
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ldr r1, =abt_stack_n
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add sp, r1, r0, asl #12
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cps #Mode_SVC
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ldr r1, =svc_stack_n
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add sp, r1, r0, asl #12
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bx lr
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#ifdef RT_USING_SMART
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.align 2
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.global enable_mmu
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enable_mmu:
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orr r0, #0x18
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mcr p15, 0, r0, c2, c0, 0 /* ttbr0 */
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mov r0, #(1 << 5) /* PD1=1 */
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mcr p15, 0, r0, c2, c0, 2 /* ttbcr */
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mov r0, #1
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mcr p15, 0, r0, c3, c0, 0 /* dacr */
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/* invalid tlb before enable mmu */
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mov r0, #0
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mcr p15, 0, r0, c8, c7, 0
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mcr p15, 0, r0, c7, c5, 0 /* iciallu */
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mcr p15, 0, r0, c7, c5, 6 /* bpiall */
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mrc p15, 0, r0, c1, c0, 0
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orr r0, #((1 << 12) | (1 << 11)) /* instruction cache, branch prediction */
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orr r0, #((1 << 2) | (1 << 0)) /* data cache, mmu enable */
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mcr p15, 0, r0, c1, c0, 0
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dsb
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isb
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mov pc, lr
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.global rt_hw_set_process_id
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rt_hw_set_process_id:
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LSL r0, r0, #8
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MCR p15, 0, r0, c13, c0, 1
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mov pc, lr
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#endif
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.global rt_hw_mmu_switch
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rt_hw_mmu_switch:
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orr r0, #0x18
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mcr p15, 0, r0, c2, c0, 0 // ttbr0
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//invalid tlb
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mov r0, #0
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mcr p15, 0, r0, c8, c7, 0
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mcr p15, 0, r0, c7, c5, 0 //iciallu
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mcr p15, 0, r0, c7, c5, 6 //bpiall
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dsb
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isb
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mov pc, lr
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.global rt_hw_mmu_tbl_get
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rt_hw_mmu_tbl_get:
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mrc p15, 0, r0, c2, c0, 0 /* ttbr0 */
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bic r0, #0x18
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mov pc, lr
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_halt:
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wfe
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b _halt
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/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */
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.section .text.isr, "ax"
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.align 5
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.globl vector_fiq
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vector_fiq:
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stmfd sp!,{r0-r7,lr}
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bl rt_hw_trap_fiq
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ldmfd sp!,{r0-r7,lr}
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subs pc, lr, #4
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.globl rt_interrupt_enter
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.globl rt_interrupt_leave
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.globl rt_thread_switch_interrupt_flag
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.globl rt_interrupt_from_thread
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.globl rt_interrupt_to_thread
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.globl rt_current_thread
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.globl vmm_thread
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.globl vmm_virq_check
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.align 5
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.globl vector_irq
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vector_irq:
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#ifdef RT_USING_SMP
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clrex
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stmfd sp!, {r0, r1}
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cps #Mode_SVC
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mov r0, sp /* svc_sp */
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mov r1, lr /* svc_lr */
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cps #Mode_IRQ
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sub lr, #4
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stmfd r0!, {r1, lr} /* svc_lr, svc_pc */
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stmfd r0!, {r2 - r12}
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ldmfd sp!, {r1, r2} /* original r0, r1 */
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stmfd r0!, {r1 - r2}
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mrs r1, spsr /* original mode */
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stmfd r0!, {r1}
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#ifdef RT_USING_SMART
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stmfd r0, {r13, r14}^ /* usr_sp, usr_lr */
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sub r0, #8
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#endif
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#ifdef RT_USING_FPU
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/* fpu context */
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vmrs r6, fpexc
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tst r6, #(1<<30)
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beq 1f
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vstmdb r0!, {d0-d15}
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vstmdb r0!, {d16-d31}
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vmrs r5, fpscr
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stmfd r0!, {r5}
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1:
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stmfd r0!, {r6}
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#endif
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/* now irq stack is clean */
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/* r0 is task svc_sp */
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/* backup r0 -> r8 */
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mov r8, r0
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cps #Mode_SVC
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mov sp, r8
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bl rt_interrupt_enter
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bl rt_hw_trap_irq
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bl rt_interrupt_leave
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mov r0, r8
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bl rt_scheduler_do_irq_switch
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b rt_hw_context_switch_exit
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#else
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stmfd sp!, {r0-r12,lr}
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bl rt_interrupt_enter
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bl rt_hw_trap_irq
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bl rt_interrupt_leave
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/* if rt_thread_switch_interrupt_flag set, jump to
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* rt_hw_context_switch_interrupt_do and don't return */
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ldr r0, =rt_thread_switch_interrupt_flag
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ldr r1, [r0]
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cmp r1, #1
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beq rt_hw_context_switch_interrupt_do
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#ifdef RT_USING_SMART
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ldmfd sp!, {r0-r12,lr}
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cps #Mode_SVC
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push {r0-r12}
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mov r7, lr
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cps #Mode_IRQ
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mrs r4, spsr
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sub r5, lr, #4
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cps #Mode_SVC
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and r6, r4, #0x1f
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cmp r6, #0x10
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bne 1f
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msr spsr_csxf, r4
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mov lr, r5
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pop {r0-r12}
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b arch_ret_to_user
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1:
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mov lr, r7
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cps #Mode_IRQ
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msr spsr_csxf, r4
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mov lr, r5
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cps #Mode_SVC
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pop {r0-r12}
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cps #Mode_IRQ
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movs pc, lr
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#else
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ldmfd sp!, {r0-r12,lr}
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subs pc, lr, #4
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#endif
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rt_hw_context_switch_interrupt_do:
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mov r1, #0 /* clear flag */
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str r1, [r0]
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mov r1, sp /* r1 point to {r0-r3} in stack */
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add sp, sp, #4*4
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ldmfd sp!, {r4-r12,lr} /* reload saved registers */
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mrs r0, spsr /* get cpsr of interrupt thread */
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sub r2, lr, #4 /* save old task's pc to r2 */
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/* Switch to SVC mode with no interrupt. If the usr mode guest is
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* interrupted, this will just switch to the stack of kernel space.
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* save the registers in kernel space won't trigger data abort. */
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msr cpsr_c, #I_Bit|F_Bit|Mode_SVC
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stmfd sp!, {r2} /* push old task's pc */
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stmfd sp!, {r4-r12,lr} /* push old task's lr,r12-r4 */
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ldmfd r1, {r1-r4} /* restore r0-r3 of the interrupt thread */
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stmfd sp!, {r1-r4} /* push old task's r0-r3 */
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stmfd sp!, {r0} /* push old task's cpsr */
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#ifdef RT_USING_SMART
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stmfd sp, {r13, r14}^ /*push usr_sp, usr_lr */
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sub sp, #8
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#endif
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#ifdef RT_USING_FPU
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/* fpu context */
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vmrs r6, fpexc
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tst r6, #(1<<30)
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beq 1f
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vstmdb sp!, {d0-d15}
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vstmdb sp!, {d16-d31}
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vmrs r5, fpscr
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stmfd sp!, {r5}
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1:
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stmfd sp!, {r6}
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#endif
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ldr r4, =rt_interrupt_from_thread
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ldr r5, [r4]
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str sp, [r5] /* store sp in preempted tasks's TCB */
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ldr r6, =rt_interrupt_to_thread
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ldr r6, [r6]
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ldr sp, [r6] /* get new task's stack pointer */
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bl rt_thread_self
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#ifdef RT_USING_SMART
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mov r4, r0
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bl lwp_aspace_switch
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mov r0, r4
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bl lwp_user_setting_restore
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#endif
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#ifdef RT_USING_FPU
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/* fpu context */
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ldmfd sp!, {r6}
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vmsr fpexc, r6
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tst r6, #(1<<30)
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beq 1f
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ldmfd sp!, {r5}
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vmsr fpscr, r5
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vldmia sp!, {d16-d31}
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vldmia sp!, {d0-d15}
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1:
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#endif
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#ifdef RT_USING_SMART
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ldmfd sp, {r13, r14}^ /*pop usr_sp, usr_lr */
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add sp, #8
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#endif
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ldmfd sp!, {r4} /* pop new task's cpsr to spsr */
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msr spsr_cxsf, r4
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#ifdef RT_USING_SMART
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and r4, #0x1f
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cmp r4, #0x10
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bne 1f
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ldmfd sp!, {r0-r12,lr}
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ldmfd sp!, {lr}
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b arch_ret_to_user
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1:
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#endif
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/* pop new task's r0-r12,lr & pc, copy spsr to cpsr */
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ldmfd sp!, {r0-r12,lr,pc}^
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#endif
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.macro push_svc_reg
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sub sp, sp, #17 * 4 /* Sizeof(struct rt_hw_exp_stack) */
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stmia sp, {r0 - r12} /* Calling r0-r12 */
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mov r0, sp
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add sp, sp, #17 * 4
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mrs r6, spsr /* Save CPSR */
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str lr, [r0, #15*4] /* Push PC */
|
|
str r6, [r0, #16*4] /* Push CPSR */
|
|
and r1, r6, #0x1f
|
|
cmp r1, #0x10
|
|
cps #Mode_SYS
|
|
streq sp, [r0, #13*4] /* Save calling SP */
|
|
streq lr, [r0, #14*4] /* Save calling PC */
|
|
cps #Mode_SVC
|
|
strne sp, [r0, #13*4] /* Save calling SP */
|
|
strne lr, [r0, #14*4] /* Save calling PC */
|
|
.endm
|
|
|
|
.align 5
|
|
.weak vector_swi
|
|
vector_swi:
|
|
push_svc_reg
|
|
bl rt_hw_trap_swi
|
|
b .
|
|
|
|
.align 5
|
|
.globl vector_undef
|
|
vector_undef:
|
|
push_svc_reg
|
|
bl rt_hw_trap_undef
|
|
cps #Mode_UND
|
|
#ifdef RT_USING_FPU
|
|
sub sp, sp, #17 * 4
|
|
ldr lr, [sp, #15*4]
|
|
ldmia sp, {r0 - r12}
|
|
add sp, sp, #17 * 4
|
|
movs pc, lr
|
|
#endif
|
|
b .
|
|
|
|
.align 5
|
|
.globl vector_pabt
|
|
vector_pabt:
|
|
push_svc_reg
|
|
#ifdef RT_USING_SMART
|
|
/* cp Mode_ABT stack to SVC */
|
|
sub sp, sp, #17 * 4 /* Sizeof(struct rt_hw_exp_stack) */
|
|
mov lr, r0
|
|
ldmia lr, {r0 - r12}
|
|
stmia sp, {r0 - r12}
|
|
add r1, lr, #13 * 4
|
|
add r2, sp, #13 * 4
|
|
ldmia r1, {r4 - r7}
|
|
stmia r2, {r4 - r7}
|
|
mov r0, sp
|
|
bl rt_hw_trap_pabt
|
|
/* return to user */
|
|
ldr lr, [sp, #16*4] /* orign spsr */
|
|
msr spsr_cxsf, lr
|
|
ldr lr, [sp, #15*4] /* orign pc */
|
|
ldmia sp, {r0 - r12}
|
|
add sp, #17 * 4
|
|
b arch_ret_to_user
|
|
#else
|
|
bl rt_hw_trap_pabt
|
|
b .
|
|
#endif
|
|
|
|
.align 5
|
|
.globl vector_dabt
|
|
vector_dabt:
|
|
push_svc_reg
|
|
#ifdef RT_USING_SMART
|
|
/* cp Mode_ABT stack to SVC */
|
|
sub sp, sp, #17 * 4 /* Sizeof(struct rt_hw_exp_stack) */
|
|
mov lr, r0
|
|
ldmia lr, {r0 - r12}
|
|
stmia sp, {r0 - r12}
|
|
add r1, lr, #13 * 4
|
|
add r2, sp, #13 * 4
|
|
ldmia r1, {r4 - r7}
|
|
stmia r2, {r4 - r7}
|
|
mov r0, sp
|
|
bl rt_hw_trap_dabt
|
|
/* return to user */
|
|
ldr lr, [sp, #16*4] /* orign spsr */
|
|
msr spsr_cxsf, lr
|
|
ldr lr, [sp, #15*4] /* orign pc */
|
|
ldmia sp, {r0 - r12}
|
|
add sp, #17 * 4
|
|
b arch_ret_to_user
|
|
#else
|
|
bl rt_hw_trap_dabt
|
|
b .
|
|
#endif
|
|
|
|
.align 5
|
|
.globl vector_resv
|
|
vector_resv:
|
|
push_svc_reg
|
|
bl rt_hw_trap_resv
|
|
b .
|
|
|
|
.global rt_hw_clz
|
|
rt_hw_clz:
|
|
clz r0, r0
|
|
bx lr
|
|
|
|
#ifdef RT_USING_SMP
|
|
|
|
.global rt_secondary_cpu_entry
|
|
rt_secondary_cpu_entry:
|
|
#ifdef RT_USING_SMART
|
|
ldr r0, =_reset
|
|
adr r5, _reset
|
|
sub r5, r5, r0
|
|
|
|
ldr lr, =after_enable_mmu_n
|
|
ldr r0, =init_mtbl
|
|
add r0, r5
|
|
b enable_mmu
|
|
|
|
after_enable_mmu_n:
|
|
ldr r0, =MMUTable
|
|
add r0, r5
|
|
bl rt_hw_mmu_switch
|
|
#endif
|
|
|
|
#ifdef RT_USING_FPU
|
|
mov r4, #0xfffffff
|
|
mcr p15, 0, r4, c1, c0, 2
|
|
#endif
|
|
|
|
mrc p15, 0, r1, c1, c0, 1
|
|
mov r0, #(1<<6)
|
|
orr r1, r0
|
|
mcr p15, 0, r1, c1, c0, 1 /* enable smp */
|
|
|
|
mrc p15, 0, r0, c1, c0, 0
|
|
bic r0, #(1<<13)
|
|
mcr p15, 0, r0, c1, c0, 0
|
|
|
|
bl stack_setup
|
|
|
|
/* initialize the mmu table and enable mmu */
|
|
#ifndef RT_USING_SMART
|
|
bl rt_hw_mmu_init
|
|
#endif
|
|
|
|
b rt_hw_secondary_cpu_bsp_start
|
|
#endif
|
|
|
|
#ifndef RT_CPUS_NR
|
|
#define RT_CPUS_NR 1
|
|
#endif
|
|
|
|
.bss
|
|
.align 3 /* align to 2~3=8 */
|
|
svc_stack_n:
|
|
.space (RT_CPUS_NR << 12)
|
|
svc_stack_n_limit:
|
|
|
|
irq_stack_n:
|
|
.space (RT_CPUS_NR << 12)
|
|
|
|
und_stack_n:
|
|
.space (RT_CPUS_NR << 12)
|
|
|
|
abt_stack_n:
|
|
.space (RT_CPUS_NR << 12)
|