107 lines
3.7 KiB
C
107 lines
3.7 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-12-25 zylx first version
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*/
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#ifndef __DRV_ETH_H__
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#define __DRV_ETH_H__
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#include <rtthread.h>
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#include <rthw.h>
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#include <rtdevice.h>
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#include <board.h>
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/* The PHY basic control register */
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#define PHY_BASIC_CONTROL_REG 0x00U
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#define PHY_RESET_MASK (1<<15)
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#define PHY_AUTO_NEGOTIATION_MASK (1<<12)
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/* The PHY basic status register */
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#define PHY_BASIC_STATUS_REG 0x01U
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#define PHY_LINKED_STATUS_MASK (1<<2)
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#define PHY_AUTONEGO_COMPLETE_MASK (1<<5)
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/* The PHY ID one register */
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#define PHY_ID1_REG 0x02U
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/* The PHY ID two register */
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#define PHY_ID2_REG 0x03U
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/* The PHY auto-negotiate advertise register */
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#define PHY_AUTONEG_ADVERTISE_REG 0x04U
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#ifdef PHY_USING_LAN8720A
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/* The PHY interrupt source flag register. */
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#define PHY_INTERRUPT_FLAG_REG 0x1DU
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/* The PHY interrupt mask register. */
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#define PHY_INTERRUPT_MASK_REG 0x1EU
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#define PHY_LINK_DOWN_MASK (1<<4)
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#define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6)
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/* The PHY status register. */
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#define PHY_Status_REG 0x1FU
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#define PHY_10M_MASK (1<<2)
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#define PHY_100M_MASK (1<<3)
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#define PHY_FULL_DUPLEX_MASK (1<<4)
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#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
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#define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK)
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#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
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#elif defined(PHY_USING_DM9161CEP)
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#define PHY_Status_REG 0x11U
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#define PHY_10M_MASK ((1<<12) || (1<<13))
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#define PHY_100M_MASK ((1<<14) || (1<<15))
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#define PHY_FULL_DUPLEX_MASK ((1<<15) || (1<<13))
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#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
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#define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK)
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#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
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/* The PHY interrupt source flag register. */
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#define PHY_INTERRUPT_FLAG_REG 0x15U
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/* The PHY interrupt mask register. */
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#define PHY_INTERRUPT_MASK_REG 0x15U
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#define PHY_LINK_CHANGE_FLAG (1<<2)
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#define PHY_LINK_CHANGE_MASK (1<<9)
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#define PHY_INT_MASK 0
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#elif defined(PHY_USING_DP83848C)
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#define PHY_Status_REG 0x10U
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#define PHY_10M_MASK (1<<1)
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#define PHY_FULL_DUPLEX_MASK (1<<2)
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#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
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#define PHY_Status_SPEED_100M(sr) (!PHY_Status_SPEED_10M(sr))
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#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
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/* The PHY interrupt source flag register. */
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#define PHY_INTERRUPT_FLAG_REG 0x12U
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#define PHY_LINK_CHANGE_FLAG (1<<13)
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/* The PHY interrupt control register. */
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#define PHY_INTERRUPT_CTRL_REG 0x11U
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#define PHY_INTERRUPT_EN ((1<<0)|(1<<1))
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/* The PHY interrupt mask register. */
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#define PHY_INTERRUPT_MASK_REG 0x12U
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#define PHY_INT_MASK (1<<5)
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#endif
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#ifdef PHY_USING_LAN8742A
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/* The PHY interrupt source flag register. */
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#define PHY_INTERRUPT_FLAG_REG 0x1DU
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/* The PHY interrupt mask register. */
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#define PHY_INTERRUPT_MASK_REG 0x1EU
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#define PHY_LINK_DOWN_MASK (1<<4)
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#define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6)
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/* The PHY status register. */
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#define PHY_Status_REG 0x1FU
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#define PHY_10M_MASK (1<<2)
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#define PHY_100M_MASK (1<<3)
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#define PHY_FULL_DUPLEX_MASK (1<<4)
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#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
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#define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK)
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#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
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#endif /* PHY_USING_LAN8742A */
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#endif /* __DRV_ETH_H__ */
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