161 lines
4.4 KiB
ArmAsm
161 lines
4.4 KiB
ArmAsm
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;/*
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; * Copyright (c) 2006-2022, RT-Thread Development Team
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; *
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; * SPDX-License-Identifier: Apache-2.0
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; *
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; * Change Logs:
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; * Date Author Notes
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; * 2009-01-20 Bernard first version
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; * 2011-07-22 Bernard added thumb mode porting
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; */
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Mode_USR EQU 0x10
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Mode_FIQ EQU 0x11
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Mode_IRQ EQU 0x12
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Mode_SVC EQU 0x13
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Mode_ABT EQU 0x17
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Mode_UND EQU 0x1B
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Mode_SYS EQU 0x1F
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I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
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F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
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NOINT EQU 0xc0 ; disable interrupt in psr
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AREA |.text|, CODE, READONLY, ALIGN=2
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ARM
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REQUIRE8
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PRESERVE8
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;/*
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; * rt_base_t rt_hw_interrupt_disable();
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; */
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rt_hw_interrupt_disable PROC
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EXPORT rt_hw_interrupt_disable
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MRS r0, cpsr
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ORR r1, r0, #NOINT
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MSR cpsr_c, r1
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BX lr
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ENDP
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;/*
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; * void rt_hw_interrupt_enable(rt_base_t level);
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; */
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rt_hw_interrupt_enable PROC
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EXPORT rt_hw_interrupt_enable
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MSR cpsr_c, r0
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BX lr
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ENDP
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;/*
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; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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; * r0 --> from
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; * r1 --> to
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; */
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rt_hw_context_switch PROC
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EXPORT rt_hw_context_switch
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STMFD sp!, {lr} ; push pc (lr should be pushed in place of PC)
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STMFD sp!, {r0-r12, lr} ; push lr & register file
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MRS r4, cpsr
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TST lr, #0x01
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BEQ _ARM_MODE
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ORR r4, r4, #0x20 ; it's thumb code
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_ARM_MODE
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STMFD sp!, {r4} ; push cpsr
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STR sp, [r0] ; store sp in preempted tasks TCB
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LDR sp, [r1] ; get new task stack pointer
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LDMFD sp!, {r4} ; pop new task cpsr to spsr
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MSR spsr_cxsf, r4
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BIC r4, r4, #0x20 ; must be ARM mode
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MSR cpsr_cxsf, r4
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LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr
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ENDP
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;/*
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; * void rt_hw_context_switch_to(rt_uint32 to);
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; * r0 --> to
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; */
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rt_hw_context_switch_to PROC
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EXPORT rt_hw_context_switch_to
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LDR sp, [r0] ; get new task stack pointer
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LDMFD sp!, {r4} ; pop new task cpsr to spsr
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MSR spsr_cxsf, r4
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BIC r4, r4, #0x20 ; must be ARM mode
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MSR cpsr_cxsf, r4
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LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr
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ENDP
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;/*
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; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
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; */
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IMPORT rt_thread_switch_interrupt_flag
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IMPORT rt_interrupt_from_thread
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IMPORT rt_interrupt_to_thread
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rt_hw_context_switch_interrupt PROC
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EXPORT rt_hw_context_switch_interrupt
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LDR r2, =rt_thread_switch_interrupt_flag
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LDR r3, [r2]
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CMP r3, #1
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BEQ _reswitch
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MOV r3, #1 ; set rt_thread_switch_interrupt_flag to 1
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STR r3, [r2]
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LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
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STR r0, [r2]
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_reswitch
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LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
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STR r1, [r2]
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BX lr
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ENDP
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; /*
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; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
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; */
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rt_hw_context_switch_interrupt_do PROC
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EXPORT rt_hw_context_switch_interrupt_do
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MOV r1, #0 ; clear flag
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STR r1, [r0]
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LDMFD sp!, {r0-r12,lr}; reload saved registers
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STMFD sp!, {r0-r3} ; save r0-r3
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MOV r1, sp
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ADD sp, sp, #16 ; restore sp
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SUB r2, lr, #4 ; save old task's pc to r2
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MRS r3, spsr ; get cpsr of interrupt thread
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; switch to SVC mode and no interrupt
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MSR cpsr_c, #I_Bit:OR:F_Bit:OR:Mode_SVC
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STMFD sp!, {r2} ; push old task's pc
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STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4
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MOV r4, r1 ; Special optimised code below
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MOV r5, r3
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LDMFD r4!, {r0-r3}
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STMFD sp!, {r0-r3} ; push old task's r3-r0
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STMFD sp!, {r5} ; push old task's cpsr
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LDR r4, =rt_interrupt_from_thread
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LDR r5, [r4]
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STR sp, [r5] ; store sp in preempted tasks's TCB
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LDR r6, =rt_interrupt_to_thread
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LDR r6, [r6]
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LDR sp, [r6] ; get new task's stack pointer
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LDMFD sp!, {r4} ; pop new task's cpsr to spsr
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MSR spsr_cxsf, r4
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BIC r4, r4, #0x20 ; must be ARM mode
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MSR cpsr_cxsf, r4
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LDMFD sp!, {r0-r12,lr,pc}^ ; pop new task's r0-r12,lr & pc, copy spsr to cpsr
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ENDP
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END
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