/** ****************************************************************************** * @file stm32f0xx_rcc.h * @author MCD Application Team * @version V1.5.1 * @date 13-October-2021 * @brief This file contains all the functions prototypes for the RCC * firmware library. ****************************************************************************** * @attention * * Copyright (c) 2014 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F0XX_RCC_H #define __STM32F0XX_RCC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f0xx.h" /** @addtogroup STM32F0xx_StdPeriph_Driver * @{ */ /** @addtogroup RCC * @{ */ /* Exported types ------------------------------------------------------------*/ typedef struct { uint32_t SYSCLK_Frequency; uint32_t HCLK_Frequency; uint32_t PCLK_Frequency; uint32_t ADCCLK_Frequency; uint32_t CECCLK_Frequency; uint32_t I2C1CLK_Frequency; uint32_t USART1CLK_Frequency; uint32_t USART2CLK_Frequency; /*!< Only applicable for STM32F072 and STM32F091 devices */ uint32_t USART3CLK_Frequency; /*!< Only applicable for STM32F091 devices */ uint32_t USBCLK_Frequency; /*!< Only applicable for STM32F072 devices */ }RCC_ClocksTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup RCC_Exported_Constants * @{ */ /** @defgroup RCC_HSE_configuration * @{ */ #define RCC_HSE_OFF ((uint8_t)0x00) #define RCC_HSE_ON ((uint8_t)0x01) #define RCC_HSE_Bypass ((uint8_t)0x05) #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ ((HSE) == RCC_HSE_Bypass)) /** * @} */ /** @defgroup RCC_PLL_Clock_Source * @{ */ #define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2 #define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_HSE_PREDIV /* Old HSEPREDIV1 bit definition, maintained for legacy purpose */ #define RCC_PLLSource_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< Only applicable for STM32F072 devices */ #define RCC_PLLSource_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV /*!< Only applicable for STM32F072 devices */ #define RCC_PLLSource_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< Only applicable for STM32F072 devices */ #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ ((SOURCE) == RCC_PLLSource_HSI48) || \ ((SOURCE) == RCC_PLLSource_HSI) || \ ((SOURCE) == RCC_PLLSource_HSE) || \ ((SOURCE) == RCC_PLLSource_PREDIV1)) /** * @} */ /** @defgroup RCC_PLL_Multiplication_Factor * @{ */ #define RCC_PLLMul_2 RCC_CFGR_PLLMULL2 #define RCC_PLLMul_3 RCC_CFGR_PLLMULL3 #define RCC_PLLMul_4 RCC_CFGR_PLLMULL4 #define RCC_PLLMul_5 RCC_CFGR_PLLMULL5 #define RCC_PLLMul_6 RCC_CFGR_PLLMULL6 #define RCC_PLLMul_7 RCC_CFGR_PLLMULL7 #define RCC_PLLMul_8 RCC_CFGR_PLLMULL8 #define RCC_PLLMul_9 RCC_CFGR_PLLMULL9 #define RCC_PLLMul_10 RCC_CFGR_PLLMULL10 #define RCC_PLLMul_11 RCC_CFGR_PLLMULL11 #define RCC_PLLMul_12 RCC_CFGR_PLLMULL12 #define RCC_PLLMul_13 RCC_CFGR_PLLMULL13 #define RCC_PLLMul_14 RCC_CFGR_PLLMULL14 #define RCC_PLLMul_15 RCC_CFGR_PLLMULL15 #define RCC_PLLMul_16 RCC_CFGR_PLLMULL16 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ ((MUL) == RCC_PLLMul_16)) /** * @} */ /** @defgroup RCC_PREDIV1_division_factor * @{ */ #define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1 #define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2 #define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3 #define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4 #define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5 #define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6 #define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7 #define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8 #define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9 #define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10 #define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11 #define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12 #define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13 #define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14 #define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15 #define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16 #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) /** * @} */ /** @defgroup RCC_System_Clock_Source * @{ */ #define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI #define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE #define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL #define RCC_SYSCLKSource_HSI48 RCC_CFGR_SW_HSI48 /*!< Only applicable for STM32F072 devices */ #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ ((SOURCE) == RCC_SYSCLKSource_HSE) || \ ((SOURCE) == RCC_SYSCLKSource_HSI48) || \ ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) /** * @} */ /** @defgroup RCC_AHB_Clock_Source * @{ */ #define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1 #define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2 #define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4 #define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8 #define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16 #define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64 #define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128 #define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256 #define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ ((HCLK) == RCC_SYSCLK_Div512)) /** * @} */ /** @defgroup RCC_APB_Clock_Source * @{ */ #define RCC_HCLK_Div1 RCC_CFGR_PPRE_DIV1 #define RCC_HCLK_Div2 RCC_CFGR_PPRE_DIV2 #define RCC_HCLK_Div4 RCC_CFGR_PPRE_DIV4 #define RCC_HCLK_Div8 RCC_CFGR_PPRE_DIV8 #define RCC_HCLK_Div16 RCC_CFGR_PPRE_DIV16 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ ((PCLK) == RCC_HCLK_Div16)) /** * @} */ /** @defgroup RCC_ADC_clock_source * @{ */ /* These defines are obsolete and kept for legacy purpose only. Proper ADC clock selection is done within ADC driver by mean of the ADC_ClockModeConfig() function */ #define RCC_ADCCLK_HSI14 ((uint32_t)0x00000000) #define RCC_ADCCLK_PCLK_Div2 ((uint32_t)0x01000000) #define RCC_ADCCLK_PCLK_Div4 ((uint32_t)0x01004000) #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADCCLK_HSI14) || ((ADCCLK) == RCC_ADCCLK_PCLK_Div2) || \ ((ADCCLK) == RCC_ADCCLK_PCLK_Div4)) /** * @} */ /** @defgroup RCC_CEC_clock_source * @{ */ #define RCC_CECCLK_HSI_Div244 ((uint32_t)0x00000000) #define RCC_CECCLK_LSE RCC_CFGR3_CECSW #define IS_RCC_CECCLK(CECCLK) (((CECCLK) == RCC_CECCLK_HSI_Div244) || ((CECCLK) == RCC_CECCLK_LSE)) /** * @} */ /** @defgroup RCC_I2C_clock_source * @{ */ #define RCC_I2C1CLK_HSI ((uint32_t)0x00000000) #define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW #define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK)) /** * @} */ /** @defgroup RCC_USB_clock_source * @brief Applicable only for STM32F072 devices * @{ */ #define RCC_USBCLK_HSI48 ((uint32_t)0x00000000) #define RCC_USBCLK_PLLCLK RCC_CFGR3_USBSW #define IS_RCC_USBCLK(USBCLK) (((USBCLK) == RCC_USBCLK_HSI48) || ((USBCLK) == RCC_USBCLK_PLLCLK)) /** * @} */ /** @defgroup RCC_USART_clock_source * @{ */ #define RCC_USART1CLK_PCLK ((uint32_t)0x10000000) #define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001) #define RCC_USART1CLK_LSE ((uint32_t)0x10000002) #define RCC_USART1CLK_HSI ((uint32_t)0x10000003) #define RCC_USART2CLK_PCLK ((uint32_t)0x20000000) /*!< Only applicable for STM32F072 and STM32F091 devices */ #define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000) /*!< Only applicable for STM32F072 and STM32F091 devices */ #define RCC_USART2CLK_LSE ((uint32_t)0x20020000) /*!< Only applicable for STM32F072 and STM32F091 devices */ #define RCC_USART2CLK_HSI ((uint32_t)0x20030000) /*!< Only applicable for STM32F072 and STM32F091 devices */ #define RCC_USART3CLK_PCLK ((uint32_t)0x30000000) /*!< Only applicable for STM32F091 devices */ #define RCC_USART3CLK_SYSCLK ((uint32_t)0x30040000) /*!< Only applicable for STM32F091 devices */ #define RCC_USART3CLK_LSE ((uint32_t)0x30080000) /*!< Only applicable for STM32F091 devices */ #define RCC_USART3CLK_HSI ((uint32_t)0x300C0000) /*!< Only applicable for STM32F091 devices */ #define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || \ ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \ ((USARTCLK) == RCC_USART1CLK_LSE) || \ ((USARTCLK) == RCC_USART1CLK_HSI) || \ ((USARTCLK) == RCC_USART2CLK_PCLK) || \ ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \ ((USARTCLK) == RCC_USART2CLK_LSE) || \ ((USARTCLK) == RCC_USART2CLK_HSI)|| \ ((USARTCLK) == RCC_USART3CLK_PCLK) || \ ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \ ((USARTCLK) == RCC_USART3CLK_LSE) || \ ((USARTCLK) == RCC_USART3CLK_HSI)) /** * @} */ /** @defgroup RCC_Interrupt_Source * @{ */ #define RCC_IT_LSIRDY ((uint8_t)0x01) #define RCC_IT_LSERDY ((uint8_t)0x02) #define RCC_IT_HSIRDY ((uint8_t)0x04) #define RCC_IT_HSERDY ((uint8_t)0x08) #define RCC_IT_PLLRDY ((uint8_t)0x10) #define RCC_IT_HSI14RDY ((uint8_t)0x20) #define RCC_IT_HSI48RDY ((uint8_t)0x40) /*!< Only applicable for STM32F072 devices */ #define RCC_IT_CSS ((uint8_t)0x80) #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_HSI14RDY) || \ ((IT) == RCC_IT_CSS) || ((IT) == RCC_IT_HSI48RDY)) #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) /** * @} */ /** @defgroup RCC_LSE_Configuration * @{ */ #define RCC_LSE_OFF ((uint32_t)0x00000000) #define RCC_LSE_ON RCC_BDCR_LSEON #define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP)) #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ ((LSE) == RCC_LSE_Bypass)) /** * @} */ /** @defgroup RCC_RTC_Clock_Source * @{ */ #define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE #define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI #define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ ((SOURCE) == RCC_RTCCLKSource_LSI) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div32)) /** * @} */ /** @defgroup RCC_LSE_Drive_Configuration * @{ */ #define RCC_LSEDrive_Low ((uint32_t)0x00000000) #define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0 #define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1 #define RCC_LSEDrive_High RCC_BDCR_LSEDRV #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \ ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High)) /** * @} */ /** @defgroup RCC_AHB_Peripherals * @{ */ #define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN #define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN #define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN #define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN #define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN /*!< Only applicable for STM32F072 and STM32F091 devices */ #define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN #define RCC_AHBPeriph_TS RCC_AHBENR_TSEN #define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN #define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN #define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN #define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN #define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFA8) == 0x00) && ((PERIPH) != 0x00)) #define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFA8) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /** @defgroup RCC_APB2_Peripherals * @{ */ #define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN #define RCC_APB2Periph_USART6 RCC_APB2ENR_USART6EN #define RCC_APB2Periph_USART7 RCC_APB2ENR_USART7EN #define RCC_APB2Periph_USART8 RCC_APB2ENR_USART8EN #define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN #define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN #define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN #define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN #define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN #define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN #define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN #define RCC_APB2Periph_DBGMCU RCC_APB2ENR_DBGMCUEN #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFB8A51E) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /** @defgroup RCC_APB1_Peripherals * @{ */ #define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN /*!< Only applicable for STM32F051, STM32F072 and STM32F091 devices */ #define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN #define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN #define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN /*!< Only applicable for STM32F072 devices */ #define RCC_APB1Periph_TIM14 RCC_APB1ENR_TIM14EN #define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN #define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN #define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN #define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN /*!< Only applicable for STM32F072 and STM32F091 devices */ #define RCC_APB1Periph_USART4 RCC_APB1ENR_USART4EN /*!< Only applicable for STM32F072 and STM32F091 devices */ #define RCC_APB1Periph_USART5 RCC_APB1ENR_USART5EN /*!< Only applicable for STM32F091 devices */ #define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN #define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN #define RCC_APB1Periph_USB RCC_APB1ENR_USBEN /*!< Only applicable for STM32F072 and STM32F042 devices */ #define RCC_APB1Periph_CAN RCC_APB1ENR_CANEN /*!< Only applicable for STM32F072, STM32F042 and STM32F091 devices */ #define RCC_APB1Periph_CRS RCC_APB1ENR_CRSEN /*!< Only applicable for STM32F072, STM32F042 and STM32F091 devices */ #define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN #define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN /*!< Only applicable for STM32F051, STM32F072 and STM32F091 devices */ #define RCC_APB1Periph_CEC RCC_APB1ENR_CECEN /*!< Only applicable for STM32F051, STM32F042, STM32F072 and STM32F091 devices */ #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x8581B6CC) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /** @defgroup RCC_MCO_Clock_Source * @{ */ #define RCC_MCOSource_NoClock ((uint8_t)0x00) #define RCC_MCOSource_HSI14 ((uint8_t)0x01) #define RCC_MCOSource_LSI ((uint8_t)0x02) #define RCC_MCOSource_LSE ((uint8_t)0x03) #define RCC_MCOSource_SYSCLK ((uint8_t)0x04) #define RCC_MCOSource_HSI ((uint8_t)0x05) #define RCC_MCOSource_HSE ((uint8_t)0x06) #define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07) #define RCC_MCOSource_HSI48 ((uint8_t)0x08) /*!< Only applicable for STM32F072 devices */ #define RCC_MCOSource_PLLCLK ((uint8_t)0x87) #define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_HSI14) || \ ((SOURCE) == RCC_MCOSource_SYSCLK) || ((SOURCE) == RCC_MCOSource_HSI) || \ ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK_Div2)|| \ ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_HSI48) || \ ((SOURCE) == RCC_MCOSource_PLLCLK) || ((SOURCE) == RCC_MCOSource_LSE)) /** * @} */ /** @defgroup RCC_MCOPrescaler * @{ */ #if !defined (STM32F051) #define RCC_MCOPrescaler_1 RCC_CFGR_MCO_PRE_1 #define RCC_MCOPrescaler_2 RCC_CFGR_MCO_PRE_2 #define RCC_MCOPrescaler_4 RCC_CFGR_MCO_PRE_4 #define RCC_MCOPrescaler_8 RCC_CFGR_MCO_PRE_8 #define RCC_MCOPrescaler_16 RCC_CFGR_MCO_PRE_16 #define RCC_MCOPrescaler_32 RCC_CFGR_MCO_PRE_32 #define RCC_MCOPrescaler_64 RCC_CFGR_MCO_PRE_64 #define RCC_MCOPrescaler_128 RCC_CFGR_MCO_PRE_128 #define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1) || \ ((PRESCALER) == RCC_MCOPrescaler_2) || \ ((PRESCALER) == RCC_MCOPrescaler_4) || \ ((PRESCALER) == RCC_MCOPrescaler_8) || \ ((PRESCALER) == RCC_MCOPrescaler_16) || \ ((PRESCALER) == RCC_MCOPrescaler_32) || \ ((PRESCALER) == RCC_MCOPrescaler_64) || \ ((PRESCALER) == RCC_MCOPrescaler_128)) #endif /* STM32F051 */ /** * @} */ /** @defgroup RCC_Flag * @{ */ #define RCC_FLAG_HSIRDY ((uint8_t)0x01) #define RCC_FLAG_HSERDY ((uint8_t)0x11) #define RCC_FLAG_PLLRDY ((uint8_t)0x19) #define RCC_FLAG_LSERDY ((uint8_t)0x21) #define RCC_FLAG_LSIRDY ((uint8_t)0x41) #define RCC_FLAG_V18PWRRSTF ((uint8_t)0x57) #define RCC_FLAG_OBLRST ((uint8_t)0x59) #define RCC_FLAG_PINRST ((uint8_t)0x5A) #define RCC_FLAG_PORRST ((uint8_t)0x5B) #define RCC_FLAG_SFTRST ((uint8_t)0x5C) #define RCC_FLAG_IWDGRST ((uint8_t)0x5D) #define RCC_FLAG_WWDGRST ((uint8_t)0x5E) #define RCC_FLAG_LPWRRST ((uint8_t)0x5F) #define RCC_FLAG_HSI14RDY ((uint8_t)0x61) #define RCC_FLAG_HSI48RDY ((uint8_t)0x71) /*!< Only applicable for STM32F072 devices */ #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \ ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST) || \ ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST) || \ ((FLAG) == RCC_FLAG_HSI14RDY)|| ((FLAG) == RCC_FLAG_HSI48RDY)|| \ ((FLAG) == RCC_FLAG_V18PWRRSTF)) #define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) #define IS_RCC_HSI14_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* Function used to set the RCC clock configuration to the default reset state */ void RCC_DeInit(void); /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ void RCC_HSEConfig(uint8_t RCC_HSE); ErrorStatus RCC_WaitForHSEStartUp(void); void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); void RCC_HSICmd(FunctionalState NewState); void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue); void RCC_HSI14Cmd(FunctionalState NewState); void RCC_HSI14ADCRequestCmd(FunctionalState NewState); void RCC_LSEConfig(uint32_t RCC_LSE); void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive); void RCC_LSICmd(FunctionalState NewState); void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); void RCC_PLLCmd(FunctionalState NewState); void RCC_HSI48Cmd(FunctionalState NewState); /*!< Only applicable for STM32F072 devices */ uint32_t RCC_GetHSI48CalibrationValue(void); /*!< Only applicable for STM32F072 devices */ void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div); void RCC_ClockSecuritySystemCmd(FunctionalState NewState); #ifdef STM32F051 void RCC_MCOConfig(uint8_t RCC_MCOSource); #else void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler); #endif /* STM32F051 */ /* System, AHB and APB busses clocks configuration functions ******************/ void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); uint8_t RCC_GetSYSCLKSource(void); void RCC_HCLKConfig(uint32_t RCC_SYSCLK); void RCC_PCLKConfig(uint32_t RCC_HCLK); void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK); /* This function is obsolete. For proper ADC clock selection, refer to ADC_ClockModeConfig() in the ADC driver */ void RCC_CECCLKConfig(uint32_t RCC_CECCLK); void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK); void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK); void RCC_USBCLKConfig(uint32_t RCC_USBCLK); /*!< Only applicable for STM32F042 and STM32F072 devices */ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); /* Peripheral clocks configuration functions **********************************/ void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); void RCC_RTCCLKCmd(FunctionalState NewState); void RCC_BackupResetCmd(FunctionalState NewState); void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); /* Interrupts and flags management functions **********************************/ void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); void RCC_ClearFlag(void); ITStatus RCC_GetITStatus(uint8_t RCC_IT); void RCC_ClearITPendingBit(uint8_t RCC_IT); #ifdef __cplusplus } #endif #endif /* __STM32F0XX_RCC_H */ /** * @} */ /** * @} */