Pcie_brige_test/Project Logs for Pcie_Brige.../PCIE_Brige_PCB PCB ECO 2022...

49 lines
2.0 KiB
Plaintext

Added Component: Designator=H1(PlatedThrHole)
Added Component: Designator=H2(PlatedThrHole)
Added Component: Designator=H3(PlatedThrHole)
Added Component: Designator=H4(PlatedThrHole)
Added Pin To Net: NetName=GND Pin=H1-1
Added Pin To Net: NetName=GND Pin=H1-1
Added Pin To Net: NetName=GND Pin=H1-1
Added Pin To Net: NetName=GND Pin=H1-1
Added Pin To Net: NetName=GND Pin=H1-1
Added Pin To Net: NetName=GND Pin=H1-1
Added Pin To Net: NetName=GND Pin=H1-1
Added Pin To Net: NetName=GND Pin=H1-1
Added Pin To Net: NetName=GND Pin=H1-1
Added Pin To Net: NetName=GND Pin=H2-1
Added Pin To Net: NetName=GND Pin=H2-1
Added Pin To Net: NetName=GND Pin=H2-1
Added Pin To Net: NetName=GND Pin=H2-1
Added Pin To Net: NetName=GND Pin=H2-1
Added Pin To Net: NetName=GND Pin=H2-1
Added Pin To Net: NetName=GND Pin=H2-1
Added Pin To Net: NetName=GND Pin=H2-1
Added Pin To Net: NetName=GND Pin=H2-1
Added Pin To Net: NetName=GND Pin=H3-1
Added Pin To Net: NetName=GND Pin=H3-1
Added Pin To Net: NetName=GND Pin=H3-1
Added Pin To Net: NetName=GND Pin=H3-1
Added Pin To Net: NetName=GND Pin=H3-1
Added Pin To Net: NetName=GND Pin=H3-1
Added Pin To Net: NetName=GND Pin=H3-1
Added Pin To Net: NetName=GND Pin=H3-1
Added Pin To Net: NetName=GND Pin=H3-1
Added Pin To Net: NetName=GND Pin=H4-1
Added Pin To Net: NetName=GND Pin=H4-1
Added Pin To Net: NetName=GND Pin=H4-1
Added Pin To Net: NetName=GND Pin=H4-1
Added Pin To Net: NetName=GND Pin=H4-1
Added Pin To Net: NetName=GND Pin=H4-1
Added Pin To Net: NetName=GND Pin=H4-1
Added Pin To Net: NetName=GND Pin=H4-1
Added Pin To Net: NetName=GND Pin=H4-1
Added Pin To Net: NetName=PCIE_SW_VDDR_3V3 Pin=U1-D14
Added Member To Class: ClassName=Pcie_Brige_pwr Member=Component H1 PlatedThrHole
Added Member To Class: ClassName=Pcie_Brige_pwr Member=Component H2 PlatedThrHole
Added Member To Class: ClassName=Pcie_Brige_pwr Member=Component H3 PlatedThrHole
Added Member To Class: ClassName=Pcie_Brige_pwr Member=Component H4 PlatedThrHole
Added Room: Name=Pcie_Brige_Cfg
Added Room: Name=Pcie_Brige_Core
Added Room: Name=Pcie_Brige_pwr