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update to hal1.8.3

master
ThinkPad-T460P 2020-12-16 12:02:47 +08:00
parent b28818536a
commit 68e8de8642
49 changed files with 3213 additions and 1381 deletions
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2
.cproject
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@ -10,6 +10,7 @@
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
@ -103,6 +104,7 @@
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">

76
.mxproject
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File diff suppressed because one or more lines are too long

1
.project
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@ -29,5 +29,6 @@
<nature>com.st.stm32cube.ide.mcu.MCURootProjectNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
<nature>com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature</nature>
</natures>
</projectDescription>

42
Core/Inc/stm32f1xx_hal_conf.h
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@ -83,11 +83,11 @@
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)12000000) /*!< Value of the External oscillator in Hz */
#define HSE_VALUE 12000000U /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */
#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
@ -96,7 +96,7 @@
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
@ -113,11 +113,11 @@
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
#define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
/* Tip: To avoid modifying this file each time you need to use different HSE,
@ -127,10 +127,10 @@
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority (lowest by default) */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define VDD_VALUE 3300U /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY 0U /*!< tick interrupt priority (lowest by default) */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 1U
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
@ -168,30 +168,30 @@
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
#define MAC_ADDR0 2
#define MAC_ADDR1 0
#define MAC_ADDR2 0
#define MAC_ADDR3 0
#define MAC_ADDR4 0
#define MAC_ADDR5 0
#define MAC_ADDR0 2U
#define MAC_ADDR1 0U
#define MAC_ADDR2 0U
#define MAC_ADDR3 0U
#define MAC_ADDR4 0U
#define MAC_ADDR5 0U
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB ((uint32_t)8) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
#define ETH_RXBUFNB 8U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
/* DP83848_PHY_ADDRESS Address*/
#define DP83848_PHY_ADDRESS 0x01U
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
#define PHY_RESET_DELAY 0x000000FFU
/* PHY Configuration delay */
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
#define PHY_CONFIG_DELAY 0x00000FFFU
#define PHY_READ_TO ((uint32_t)0x0000FFFF)
#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
#define PHY_READ_TO 0x0000FFFFU
#define PHY_WRITE_TO 0x0000FFFFU
/* Section 3: Common PHY Registers */

4
Core/Src/freertos.c
View File

@ -157,7 +157,7 @@ void MX_FREERTOS_Init(void) {
/* Create the queue(s) */
/* creation of uartQueue */
uartQueueHandle = osMessageQueueNew (1024, sizeof(uint8_t), &uartQueue_attributes);
uartQueueHandle = osMessageQueueNew (128, sizeof(uint8_t), &uartQueue_attributes);
/* USER CODE BEGIN RTOS_QUEUES */
/* add queues, ... */
@ -177,7 +177,7 @@ void MX_FREERTOS_Init(void) {
EventDetectHandle = osThreadNew(StartEventDetect, NULL, &EventDetect_attributes);
/* creation of CoulombRead */
CoulombReadHandle = osThreadNew(StartCoulombRead, NULL, &CoulombRead_attributes);
// CoulombReadHandle = osThreadNew(StartCoulombRead, NULL, &CoulombRead_attributes);
/* creation of StateSwitchTask */
StateSwitchTaskHandle = osThreadNew(StartStateSwitchTask, NULL, &StateSwitchTask_attributes);

4
Core/Src/i2c.c
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@ -112,7 +112,9 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle)
PB8 ------> I2C1_SCL
PB9 ------> I2C1_SDA
*/
HAL_GPIO_DeInit(GPIOB, IIC1_SCL_Pin|IIC1_SDA_Pin);
HAL_GPIO_DeInit(IIC1_SCL_GPIO_Port, IIC1_SCL_Pin);
HAL_GPIO_DeInit(IIC1_SDA_GPIO_Port, IIC1_SDA_Pin);
/* I2C1 interrupt Deinit */
HAL_NVIC_DisableIRQ(I2C1_EV_IRQn);

17
Core/Src/main.c
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@ -17,7 +17,6 @@
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "cmsis_os.h"
@ -99,7 +98,7 @@ int main(void)
MX_GPIO_Init();
MX_DMA_Init();
MX_I2C1_Init();
// MX_IWDG_Init();
MX_IWDG_Init();
MX_UART4_Init();
MX_ADC1_Init();
MX_USART1_UART_Init();
@ -139,7 +138,8 @@ void SystemClock_Config(void)
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
/** Initializes the CPU, AHB and APB busses clocks
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@ -155,7 +155,7 @@ void SystemClock_Config(void)
{
Error_Handler();
}
/** Initializes the CPU, AHB and APB busses clocks
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@ -200,12 +200,12 @@ static void MX_NVIC_Init(void)
/* RCC_IRQn interrupt configuration */
HAL_NVIC_SetPriority(RCC_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(RCC_IRQn);
/* UART4_IRQn interrupt configuration */
HAL_NVIC_SetPriority(UART4_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(UART4_IRQn);
/* OTG_FS_IRQn interrupt configuration */
HAL_NVIC_SetPriority(OTG_FS_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(OTG_FS_IRQn);
/* UART4_IRQn interrupt configuration */
HAL_NVIC_SetPriority(UART4_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(UART4_IRQn);
/* I2C1_EV_IRQn interrupt configuration */
HAL_NVIC_SetPriority(I2C1_EV_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(I2C1_EV_IRQn);
@ -218,6 +218,9 @@ static void MX_NVIC_Init(void)
/* DMA1_Channel1_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
/* USART1_IRQn interrupt configuration */
HAL_NVIC_SetPriority(USART1_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(USART1_IRQn);
}
/* USER CODE BEGIN 4 */

2
Core/Src/stm32f1xx_hal_timebase_tim.c
View File

@ -45,13 +45,11 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
uint32_t uwTimclock = 0;
uint32_t uwPrescalerValue = 0;
uint32_t pFLatency;
/*Configure the TIM1 IRQ priority */
HAL_NVIC_SetPriority(TIM1_UP_IRQn, TickPriority ,0);
/* Enable the TIM1 global Interrupt */
HAL_NVIC_EnableIRQ(TIM1_UP_IRQn);
/* Enable TIM1 clock */
__HAL_RCC_TIM1_CLK_ENABLE();

2
Core/Src/stm32f1xx_it.c
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@ -21,8 +21,6 @@
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "stm32f1xx_it.h"
#include "FreeRTOS.h"
#include "task.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */

3
Core/Src/usart.c
View File

@ -118,9 +118,6 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USART1 interrupt Init */
HAL_NVIC_SetPriority(USART1_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(USART1_IRQn);
/* USER CODE BEGIN USART1_MspInit 1 */
/* USER CODE END USART1_MspInit 1 */

38
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f107xc.h
View File

@ -1330,6 +1330,11 @@ typedef struct
/* Reset and Clock Control */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
*/
#define RCC_PLL2_SUPPORT /*!< Support PLL2 */
#define RCC_PLLI2S_SUPPORT
/******************** Bit definition for RCC_CR register ********************/
#define RCC_CR_HSION_Pos (0U)
@ -1363,11 +1368,6 @@ typedef struct
#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
*/
#define RCC_PLL2_SUPPORT /*!< Support PLL2 */
#define RCC_CR_PLL2ON_Pos (26U)
#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */
#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< PLL2 enable */
@ -1375,11 +1375,6 @@ typedef struct
#define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */
#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
*/
#define RCC_PLLI2S_SUPPORT /*!< Support PLL3 (PLLI2S)*/
#define RCC_CR_PLL3ON_Pos (28U)
#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */
#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< PLL3 enable */
@ -12006,7 +12001,6 @@ typedef struct
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
/****************** Bit definition for SPI_I2SPR register *******************/
#define SPI_I2SPR_I2SDIV_Pos (0U)
#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
@ -15003,8 +14997,6 @@ typedef struct
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5))
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
@ -15195,42 +15187,42 @@ typedef struct
/* Aliases for __IRQn */
#define ADC1_IRQn ADC1_2_IRQn
#define USB_LP_CAN1_RX0_IRQn CAN1_RX0_IRQn
#define USB_LP_IRQn CAN1_RX0_IRQn
#define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn
#define USB_LP_CAN1_RX0_IRQn CAN1_RX0_IRQn
#define USB_HP_IRQn CAN1_TX_IRQn
#define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn
#define DMA2_Channel4_5_IRQn DMA2_Channel4_IRQn
#define USBWakeUp_IRQn OTG_FS_WKUP_IRQn
#define CEC_IRQn OTG_FS_WKUP_IRQn
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
#define TIM9_IRQn TIM1_BRK_IRQn
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
#define TIM11_IRQn TIM1_TRG_COM_IRQn
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
#define TIM11_IRQn TIM1_TRG_COM_IRQn
#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
#define TIM10_IRQn TIM1_UP_IRQn
#define TIM6_DAC_IRQn TIM6_IRQn
/* Aliases for __IRQHandler */
#define ADC1_IRQHandler ADC1_2_IRQHandler
#define USB_LP_CAN1_RX0_IRQHandler CAN1_RX0_IRQHandler
#define USB_LP_IRQHandler CAN1_RX0_IRQHandler
#define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler
#define USB_LP_CAN1_RX0_IRQHandler CAN1_RX0_IRQHandler
#define USB_HP_IRQHandler CAN1_TX_IRQHandler
#define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler
#define DMA2_Channel4_5_IRQHandler DMA2_Channel4_IRQHandler
#define USBWakeUp_IRQHandler OTG_FS_WKUP_IRQHandler
#define CEC_IRQHandler OTG_FS_WKUP_IRQHandler
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
#define TIM9_IRQHandler TIM1_BRK_IRQHandler
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
#define TIM10_IRQHandler TIM1_UP_IRQHandler
#define TIM6_DAC_IRQHandler TIM6_IRQHandler

4
Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h
View File

@ -90,11 +90,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V4.3.1
* @brief CMSIS Device version number V4.3.2
*/
#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
#define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F1_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F1_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
|(__STM32F1_CMSIS_VERSION_SUB1 << 16)\

174
Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
View File

@ -38,7 +38,6 @@
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
/**
* @}
*/
@ -236,12 +235,12 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
#if defined(STM32G4)
#define DAC_CHIPCONNECT_DISABLE (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH)
#define DAC_CHIPCONNECT_ENABLE (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH)
#if defined(STM32G4) || defined(STM32H7)
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0)
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif
@ -306,8 +305,22 @@
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
#endif
#endif /* STM32L4 */
#if defined(STM32G0)
#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
#endif
#if defined(STM32H7)
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
@ -365,6 +378,9 @@
#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
#endif /* STM32H7 */
/**
@ -460,7 +476,9 @@
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
#endif
#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
#endif /* STM32H7 */
/**
* @}
@ -564,7 +582,14 @@
#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
#endif
#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
#endif /* STM32H7 */
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
@ -622,6 +647,10 @@
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A
#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B
#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
#endif /* STM32G4 */
#if defined(STM32H7)
@ -735,6 +764,66 @@
#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
#endif /* STM32H7 */
#if defined(STM32F3)
/** @brief Constants defining available sources associated to external events.
*/
#define HRTIM_EVENTSRC_1 (0x00000000U)
#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
/** @brief Constants defining the events that can be selected to configure the
* set/reset crossbar of a timer output
*/
#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
/** @brief Constants defining the event filtering applied to external events
* by a timer
*/
#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
/** @brief Constants defining the DLL calibration periods (in micro seconds)
*/
#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
#endif /* STM32F3 */
/**
* @}
*/
@ -874,7 +963,7 @@
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
#if defined(STM32L1) || defined(STM32L4)
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
@ -965,6 +1054,16 @@
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
#if defined(STM32H7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
#endif /* STM32H7 */
/**
* @}
*/
@ -1358,6 +1457,30 @@
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
/**
* @}
*/
@ -1380,6 +1503,13 @@
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
/**
* @}
*/
@ -1409,16 +1539,18 @@
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
#if defined(STM32F4)
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
@ -1437,6 +1569,13 @@
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
* @{
*/
#if defined(STM32G0)
#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
#endif
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
@ -1509,14 +1648,14 @@
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4)
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */
#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
/**
* @}
*/
@ -3112,9 +3251,8 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
#if defined(STM32L4)
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4)
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif
@ -3242,7 +3380,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4)
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@ -3365,7 +3503,7 @@
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
#endif
#if defined(STM32H7)
#if defined(STM32H7) || defined(STM32L5)
#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
@ -3620,9 +3758,9 @@
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32L4)
#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
#endif
#endif /* STM32L4 || STM32F4 || STM32F7 */
/**
* @}
*/

1
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h
View File

@ -57,6 +57,7 @@ typedef enum
* @}
*/
/* Exported types ------------------------------------------------------------*/
extern __IO uint32_t uwTick;
extern uint32_t uwTickPrio;
extern HAL_TickFreqTypeDef uwTickFreq;

34
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h
View File

@ -28,9 +28,7 @@ extern "C" {
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
#if defined(USE_HAL_LEGACY)
#include "Legacy/stm32_hal_legacy.h"
#endif
#include <stddef.h>
/* Exported types ------------------------------------------------------------*/
@ -108,7 +106,14 @@ typedef enum
}while (0U)
#endif /* USE_RTOS */
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __weak
#define __weak __attribute__((weak))
#endif
#ifndef __packed
#define __packed __attribute__((packed))
#endif
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
@ -119,7 +124,14 @@ typedef enum
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
@ -131,7 +143,7 @@ typedef enum
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */
#if defined (__CC_ARM) /* ARM Compiler V5*/
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
@ -143,9 +155,9 @@ typedef enum
/**
* @brief __RAM_FUNC definition
*/
#if defined ( __CC_ARM )
/* ARM Compiler
------------
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
/* ARM Compiler V4/V5 and V6
--------------------------
RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
@ -175,9 +187,9 @@ typedef enum
/**
* @brief __NOINLINE definition
*/
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
/* ARM & GNUCompiler
----------------
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
/* ARM V4/V5 and V6 & GNU Compiler
-------------------------------
*/
#define __NOINLINE __attribute__ ( (noinline) )

5
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_i2c.h
View File

@ -170,6 +170,7 @@ typedef enum
#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */
#define HAL_I2C_ERROR_SIZE 0x00000040U /*!< Size Management error */
#define HAL_I2C_ERROR_DMA_PARAM 0x00000080U /*!< DMA Parameter Error */
#define HAL_I2C_WRONG_START 0x00000200U /*!< Wrong start Error */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define HAL_I2C_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid Callback error */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
@ -181,7 +182,11 @@ typedef enum
* @brief I2C handle Structure definition
* @{
*/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
typedef struct __I2C_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
{
I2C_TypeDef *Instance; /*!< I2C registers base address */

16
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h
View File

@ -32,7 +32,7 @@ extern "C" {
* @{
*/
/** @addtogroup IWDG
/** @defgroup IWDG IWDG
* @{
*/
@ -62,9 +62,9 @@ typedef struct
IWDG_TypeDef *Instance; /*!< Register base address */
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
} IWDG_HandleTypeDef;
/**
* @}
*/
@ -84,15 +84,17 @@ typedef struct
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
* @{
@ -107,7 +109,7 @@ typedef struct
/**
* @brief Reload IWDG counter with value defined in the reload register
* (write access to IWDG_PR & IWDG_RLR registers disabled).
* (write access to IWDG_PR and IWDG_RLR registers disabled).
* @param __HANDLE__ IWDG handle
* @retval None
*/
@ -200,6 +202,8 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
*/
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
/**
* @}
*/

195
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd.h
View File

@ -203,8 +203,7 @@ typedef struct
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
~(USB_OTG_PCGCCTL_STOPCLK)
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
@ -226,7 +225,7 @@ typedef struct
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= (uint16_t)(~(__INTERRUPT__)))
#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
@ -297,19 +296,31 @@ typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t
* @}
*/
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
HAL_PCD_CallbackIDTypeDef CallbackID,
pPCD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd,
HAL_PCD_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
pPCD_DataOutStageCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
pPCD_DataInStageCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
pPCD_IsoOutIncpltCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
pPCD_IsoInIncpltCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
@ -325,6 +336,7 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
@ -349,16 +361,24 @@ void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint16_t ep_mps, uint8_t ep_type);
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint8_t *pBuf, uint32_t len);
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint8_t *pBuf, uint32_t len);
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
/**
* @}
*/
@ -384,10 +404,6 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @{
*/
#if defined (USB_OTG_FS)
#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U
#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
#endif /* defined (USB_OTG_FS) */
@ -402,10 +418,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
/** @defgroup PCD_EP0_MPS PCD EP0 MPS
* @{
*/
#define PCD_EP0MPS_64 DEP0CTL_MPS_64
#define PCD_EP0MPS_32 DEP0CTL_MPS_32
#define PCD_EP0MPS_16 DEP0CTL_MPS_16
#define PCD_EP0MPS_08 DEP0CTL_MPS_8
#define PCD_EP0MPS_64 EP_MPS_64
#define PCD_EP0MPS_32 EP_MPS_32
#define PCD_EP0MPS_16 EP_MPS_16
#define PCD_EP0MPS_08 EP_MPS_8
/**
* @}
*/
@ -489,8 +505,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wType Endpoint Type.
* @retval None
*/
#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
/**
* @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
@ -507,7 +522,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bEpNum, bDir
* @retval None
*/
#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) do { \
#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) \
do { \
if ((bDir) == 0U) \
{ \
/* OUT double buffered endpoint */ \
@ -527,8 +543,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wState new state
* @retval None
*/
#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) do { \
register uint16_t _wRegVal; \
#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
/* toggle first bit ? */ \
@ -551,8 +568,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wState new state
* @retval None
*/
#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) do { \
register uint16_t _wRegVal; \
#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
/* toggle first bit ? */ \
@ -576,8 +594,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wStatetx new state.
* @retval None
*/
#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) do { \
register uint16_t _wRegVal; \
#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
/* toggle first bit ? */ \
@ -629,10 +648,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bEpNum Endpoint Number.
* @retval TRUE = endpoint in stall condition.
*/
#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
== USB_EP_TX_STALL)
#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
== USB_EP_RX_STALL)
#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL)
#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL)
/**
* @brief set & clear EP_KIND bit.
@ -640,16 +657,18 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_SET_EP_KIND(USBx, bEpNum) do { \
register uint16_t _wRegVal; \
#define PCD_SET_EP_KIND(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \
} while(0) /* PCD_SET_EP_KIND */
#define PCD_CLEAR_EP_KIND(USBx, bEpNum) do { \
register uint16_t _wRegVal; \
#define PCD_CLEAR_EP_KIND(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
\
@ -680,16 +699,18 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) do { \
register uint16_t _wRegVal; \
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \
} while(0) /* PCD_CLEAR_RX_EP_CTR */
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) do { \
register uint16_t _wRegVal; \
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
\
@ -702,16 +723,18 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_RX_DTOG(USBx, bEpNum) do { \
register uint16_t _wEPVal; \
#define PCD_RX_DTOG(USBx, bEpNum) \
do { \
uint16_t _wEPVal; \
\
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \
} while(0) /* PCD_RX_DTOG */
#define PCD_TX_DTOG(USBx, bEpNum) do { \
register uint16_t _wEPVal; \
#define PCD_TX_DTOG(USBx, bEpNum) \
do { \
uint16_t _wEPVal; \
\
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
\
@ -723,8 +746,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) do { \
register uint16_t _wRegVal; \
#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
\
@ -734,8 +758,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
} \
} while(0) /* PCD_CLEAR_RX_DTOG */
#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) do { \
register uint16_t _wRegVal; \
#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
\
@ -752,8 +777,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bAddr Address.
* @retval None
*/
#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) do { \
register uint16_t _wRegVal; \
#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
\
@ -778,18 +804,20 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wAddr address to be set (must be word aligned).
* @retval None
*/
#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) do { \
register __IO uint16_t *_wRegVal; \
register uint32_t _wRegBase = (uint32_t)USBx; \
#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \
do { \
__IO uint16_t *_wRegVal; \
uint32_t _wRegBase = (uint32_t)USBx; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
*_wRegVal = ((wAddr) >> 1) << 1; \
} while(0) /* PCD_SET_EP_TX_ADDRESS */
#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) do { \
register __IO uint16_t *_wRegVal; \
register uint32_t _wRegBase = (uint32_t)USBx; \
#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \
do { \
__IO uint16_t *_wRegVal; \
uint32_t _wRegBase = (uint32_t)USBx; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
@ -812,7 +840,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wNBlocks no. of Blocks.
* @retval None
*/
#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) do { \
#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \
do { \
(wNBlocks) = (wCount) >> 5; \
if (((wCount) & 0x1fU) == 0U) \
{ \
@ -821,7 +850,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
*(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
} while(0) /* PCD_CALC_BLK32 */
#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) do { \
#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \
do { \
(wNBlocks) = (wCount) >> 1; \
if (((wCount) & 0x1U) != 0U) \
{ \
@ -830,7 +860,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
*(pdwReg) = (uint16_t)((wNBlocks) << 10); \
} while(0) /* PCD_CALC_BLK2 */
#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) do { \
#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \
do { \
uint32_t wNBlocks; \
if ((wCount) == 0U) \
{ \
@ -847,9 +878,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
} \
} while(0) /* PCD_SET_EP_CNT_RX_REG */
#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) do { \
register uint32_t _wRegBase = (uint32_t)(USBx); \
register __IO uint16_t *pdwReg; \
#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \
do { \
uint32_t _wRegBase = (uint32_t)(USBx); \
__IO uint16_t *pdwReg; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
@ -863,18 +895,20 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wCount Counter value.
* @retval None
*/
#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) do { \
register uint32_t _wRegBase = (uint32_t)(USBx); \
register __IO uint16_t *_wRegVal; \
#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \
do { \
uint32_t _wRegBase = (uint32_t)(USBx); \
__IO uint16_t *_wRegVal; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
*_wRegVal = (uint16_t)(wCount); \
} while(0)
#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) do { \
register uint32_t _wRegBase = (uint32_t)(USBx); \
register __IO uint16_t *_wRegVal; \
#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \
do { \
uint32_t _wRegBase = (uint32_t)(USBx); \
__IO uint16_t *_wRegVal; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
@ -897,10 +931,13 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wBuf0Addr buffer 0 address.
* @retval Counter value
*/
#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) do { \
#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \
do { \
PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \
} while(0) /* PCD_SET_EP_DBUF0_ADDR */
#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) do { \
#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \
do { \
PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \
} while(0) /* PCD_SET_EP_DBUF1_ADDR */
@ -912,7 +949,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wBuf1Addr = buffer 1 address.
* @retval None
*/
#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) do { \
#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \
do { \
PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \
PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \
} while(0) /* PCD_SET_EP_DBUF_ADDR */
@ -935,7 +973,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wCount: Counter value
* @retval None
*/
#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) do { \
#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \
do { \
if ((bDir) == 0U) \
/* OUT endpoint */ \
{ \
@ -951,8 +990,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
} \
} while(0) /* SetEPDblBuf0Count*/
#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) do { \
register uint32_t _wBase = (uint32_t)(USBx); \
#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \
do { \
uint32_t _wBase = (uint32_t)(USBx); \
__IO uint16_t *_wEPRegVal; \
\
if ((bDir) == 0U) \
@ -972,7 +1012,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
} \
} while(0) /* SetEPDblBuf1Count */
#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) do { \
#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \
do { \
PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
} while(0) /* PCD_SET_EP_DBUF_CNT */

6
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pcd_ex.h
View File

@ -53,10 +53,8 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
uint16_t ep_addr,
uint16_t ep_kind,
uint32_t pmaadress);
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
uint16_t ep_kind, uint32_t pmaadress);
void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
#endif /* defined (USB) */

6
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h
View File

@ -330,11 +330,11 @@ typedef struct
*/
#define RCC_PERIPHCLK_RTC 0x00000001U
#define RCC_PERIPHCLK_ADC 0x00000002U
#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
|| defined(STM32F107xC)
#if defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE)\
|| defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
#define RCC_PERIPHCLK_I2S2 0x00000004U
#define RCC_PERIPHCLK_I2S3 0x00000008U
#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|| defined(STM32F105xC) || defined(STM32F107xC)

115
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h
View File

@ -167,7 +167,7 @@ typedef struct
This parameter can be a value of @ref TIM_Encoder_Mode */
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC1Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@ -179,7 +179,7 @@ typedef struct
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC2Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@ -294,6 +294,26 @@ typedef enum
HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
} HAL_TIM_StateTypeDef;
/**
* @brief TIM Channel States definition
*/
typedef enum
{
HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */
HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */
} HAL_TIM_ChannelStateTypeDef;
/**
* @brief DMA Burst States definition
*/
typedef enum
{
HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
} HAL_TIM_DMABurstStateTypeDef;
/**
* @brief HAL Active channel structures definition
*/
@ -322,6 +342,9 @@ typedef struct
This array is accessed by a @ref DMA_Handle_index */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
__IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */
__IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */
__IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
@ -593,6 +616,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @}
*/
/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
* @{
*/
#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
/**
* @}
*/
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{
*/
@ -986,6 +1018,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
(__HANDLE__)->Base_MspInitCallback = NULL; \
(__HANDLE__)->Base_MspDeInitCallback = NULL; \
(__HANDLE__)->IC_MspInitCallback = NULL; \
@ -1002,7 +1043,18 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
(__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
} while(0)
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
@ -1547,6 +1599,9 @@ mode.
#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
((__STATE__) == TIM_OCNIDLESTATE_RESET))
#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
@ -1717,6 +1772,8 @@ mode.
((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
@ -1742,11 +1799,49 @@ mode.
((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP))) :\
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) :\
((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P)))
#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
(__HANDLE__)->ChannelState[3])
#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
(__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
} while(0)
#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
(__HANDLE__)->ChannelNState[3])
#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
(__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \
} while(0)
/**
* @}
*/
@ -1918,9 +2013,15 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
@ -1966,6 +2067,11 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
/* Peripheral Channel state functions ************************************************/
HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
/**
* @}
*/
@ -1985,7 +2091,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
void TIM_DMAError(DMA_HandleTypeDef *hdma);
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);

1
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h
View File

@ -223,6 +223,7 @@ void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
*/
/* Extended Peripheral State functions ***************************************/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
/**
* @}
*/

6
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h
View File

@ -537,7 +537,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
(((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
/** @brief Checks whether the specified UART interrupt has occurred or not.
/** @brief Checks whether the specified UART interrupt source is enabled or not.
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
@ -806,7 +806,7 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)
#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U)
/* UART BRR = mantissa + overflow + fraction
= (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \
@ -815,7 +815,7 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)
#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U)
#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U) + 50U) / 100U)
/* UART BRR = mantissa + overflow + fraction
= (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \

63
Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usb.h
View File

@ -81,7 +81,7 @@ typedef enum
} USB_OTG_HCStateTypeDef;
/**
* @brief USB OTG Initialization Structure definition
* @brief USB Instance Initialization Structure definition
*/
typedef struct
{
@ -94,14 +94,14 @@ typedef struct
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t speed; /*!< USB Core speed.
This parameter can be any value of @ref USB_Core_Speed_ */
This parameter can be any value of @ref USB_Core_Speed */
uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
uint32_t phy_itface; /*!< Select the used PHY interface.
This parameter can be any value of @ref USB_Core_PHY_ */
This parameter can be any value of @ref USB_Core_PHY */
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
@ -116,6 +116,7 @@ typedef struct
uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
} USB_OTG_CfgTypeDef;
typedef struct
@ -282,6 +283,10 @@ typedef struct
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */
uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */
} USB_EPTypeDef;
#endif /* defined (USB) */
@ -315,7 +320,7 @@ typedef struct
* @{
*/
#define USBD_FS_SPEED 2U
#define USBH_FS_SPEED 1U
#define USBH_FSLS_SPEED 1U
/**
* @}
*/
@ -381,10 +386,10 @@ typedef struct
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
#define DEP0CTL_MPS_64 0U
#define DEP0CTL_MPS_32 1U
#define DEP0CTL_MPS_16 2U
#define DEP0CTL_MPS_8 3U
#define EP_MPS_64 0U
#define EP_MPS_32 1U
#define EP_MPS_16 2U
#define EP_MPS_8 3U
/**
* @}
*/
@ -474,10 +479,10 @@ typedef struct
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
#define DEP0CTL_MPS_64 0U
#define DEP0CTL_MPS_32 1U
#define DEP0CTL_MPS_16 2U
#define DEP0CTL_MPS_8 3U
#define EP_MPS_64 0U
#define EP_MPS_32 1U
#define EP_MPS_16 2U
#define EP_MPS_8 3U
/**
* @}
*/
@ -550,7 +555,9 @@ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
uint8_t ch_ep_num, uint16_t len);
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
@ -575,14 +582,12 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
uint8_t ch_num,
uint8_t epnum,
uint8_t dev_address,
uint8_t speed,
uint8_t ep_type,
uint16_t mps);
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc);
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
uint8_t epnum, uint8_t dev_address, uint8_t speed,
uint8_t ep_type, uint16_t mps);
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx,
USB_OTG_HCTypeDef *hc);
uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
@ -603,8 +608,6 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num);
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);
void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len);
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);
@ -612,17 +615,25 @@ HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup);
HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src,
uint8_t ch_ep_num, uint16_t len);
void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len);
uint32_t USB_ReadInterrupts(USB_TypeDef *USBx);
uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx);
uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx);
uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt);
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
uint16_t wPMABufAddr, uint16_t wNBytes);
void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
uint16_t wPMABufAddr, uint16_t wNBytes);
#endif /* defined (USB) */
/**
* @}

18
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c
View File

@ -53,11 +53,11 @@
* @{
*/
/**
* @brief STM32F1xx HAL Driver version number V1.1.4
* @brief STM32F1xx HAL Driver version number V1.1.7
*/
#define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
#define __STM32F1xx_HAL_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */
#define __STM32F1xx_HAL_VERSION_SUB2 (0x07U) /*!< [15:8] sub2 version */
#define __STM32F1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24)\
|(__STM32F1xx_HAL_VERSION_SUB1 << 16)\
@ -322,15 +322,25 @@ uint32_t HAL_GetTickPrio(void)
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_TickFreqTypeDef prevTickFreq;
assert_param(IS_TICKFREQ(Freq));
if (uwTickFreq != Freq)
{
/* Back up uwTickFreq frequency */
prevTickFreq = uwTickFreq;
/* Update uwTickFreq global variable used by HAL_InitTick() */
uwTickFreq = Freq;
/* Apply the new tick Freq */
status = HAL_InitTick(uwTickPrio);
if (status == HAL_OK)
if (status != HAL_OK)
{
uwTickFreq = Freq;
/* Restore previous tick frequency */
uwTickFreq = prevTickFreq;
}
}

3
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c
View File

@ -1711,6 +1711,8 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
/* Disable the DMA channel (in case of DMA in circular mode or stop while */
/* DMA transfer is on going) */
if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
{
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
/* Check if DMA channel effectively disabled */
@ -1727,6 +1729,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
}
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);

15
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c
View File

@ -486,17 +486,16 @@ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
uint32_t odr;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->ODR & GPIO_Pin) != 0x00u)
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
}
/* get current Ouput Data Register value */
odr = GPIOx->ODR;
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
}
/**

435
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c
View File

@ -337,6 +337,7 @@
*/
#define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */
#define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */
#define I2C_TIMEOUT_STOP_FLAG 5U /*!< Timeout 5 ms */
#define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */
/* Private define for @ref PreviousState usage */
@ -377,6 +378,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c);
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
/* Private functions for I2C transfer IRQ handler */
@ -396,6 +398,8 @@ static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags);
static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c);
/* Private function to Convert Specific options */
static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
/**
@ -504,6 +508,10 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/*Reset I2C*/
hi2c->Instance->CR1 |= I2C_CR1_SWRST;
hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
/* Get PCLK1 frequency */
pclk1 = HAL_RCC_GetPCLK1Freq();
@ -1162,6 +1170,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
*/
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
__IO uint32_t count = 0U;
/* Init tickstart for timeout management*/
uint32_t tickstart = HAL_GetTick();
@ -1344,10 +1354,27 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
hi2c->XferCount--;
/* Wait until BTF flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U);
do
{
count--;
if (count == 0U)
{
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Re-enable IRQs */
__enable_irq();
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET);
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
@ -2567,6 +2594,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
__IO uint32_t count = 0U;
/* Init tickstart for timeout management*/
uint32_t tickstart = HAL_GetTick();
@ -2751,10 +2780,27 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
hi2c->XferCount--;
/* Wait until BTF flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U);
do
{
count--;
if (count == 0U)
{
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
/* Re-enable IRQs */
__enable_irq();
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET);
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
@ -3100,6 +3146,27 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
/* Abort the ongoing DMA */
dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmatx);
/* Prevent unused argument(s) compilation and MISRA warning */
UNUSED(dmaxferstatus);
/* Clear directly Complete callback as no XferAbortCallback is used to finalize Abort treatment */
if (hi2c->hdmatx != NULL)
{
hi2c->hdmatx->XferCpltCallback = NULL;
}
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
hi2c->XferSize = 0U;
hi2c->XferCount = 0U;
/* Disable I2C peripheral to prevent dummy data in buffer */
__HAL_I2C_DISABLE(hi2c);
return HAL_ERROR;
}
@ -3243,6 +3310,27 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
/* Abort the ongoing DMA */
dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmarx);
/* Prevent unused argument(s) compilation and MISRA warning */
UNUSED(dmaxferstatus);
/* Clear directly Complete callback as no XferAbortCallback is used to finalize Abort treatment */
if (hi2c->hdmarx != NULL)
{
hi2c->hdmarx->XferCpltCallback = NULL;
}
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
hi2c->XferSize = 0U;
hi2c->XferCount = 0U;
/* Disable I2C peripheral to prevent dummy data in buffer */
__HAL_I2C_DISABLE(hi2c);
return HAL_ERROR;
}
@ -3367,7 +3455,11 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
{
hi2c->ErrorCode = HAL_I2C_WRONG_START;
}
return HAL_TIMEOUT;
}
/* Send slave address */
@ -3469,7 +3561,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Check Busy Flag only if FIRST call of Master interface */
if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
{
/* Wait until BUSY flag is reset */
count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
@ -3568,7 +3660,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Check Busy Flag only if FIRST call of Master interface */
if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
{
/* Wait until BUSY flag is reset */
count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
@ -3734,7 +3826,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Check Busy Flag only if FIRST call of Master interface */
if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
{
/* Wait until BUSY flag is reset */
count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
@ -3859,7 +3951,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Check Busy Flag only if FIRST call of Master interface */
if ((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
{
/* Wait until BUSY flag is reset */
count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
@ -4561,11 +4653,14 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
*/
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
{
/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
/* Prevent unused argument(s) compilation warning */
UNUSED(DevAddress);
/* Abort Master transfer during Receive or Transmit process */
if (hi2c->Mode == HAL_I2C_MODE_MASTER)
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && (CurrentMode == HAL_I2C_MODE_MASTER))
{
/* Process Locked */
__HAL_LOCK(hi2c);
@ -4596,6 +4691,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA
{
/* Wrong usage of abort function */
/* This function should be used only in case of abort monitored by master device */
/* Or periphal is not in busy state, mean there is no active sequence to be abort */
return HAL_ERROR;
}
}
@ -4666,9 +4762,16 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
}
/* BTF set -------------------------------------------------------------*/
else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
{
if (CurrentMode == HAL_I2C_MODE_MASTER)
{
I2C_MasterTransmit_BTF(hi2c);
}
else /* HAL_I2C_MODE_MEM */
{
I2C_MemoryTransmit_TXE_BTF(hi2c);
}
}
else
{
/* Do nothing */
@ -4782,6 +4885,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
uint32_t itsources = READ_REG(hi2c->Instance->CR2);
uint32_t error = HAL_I2C_ERROR_NONE;
HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
/* I2C Bus error interrupt occurred ----------------------------------------*/
if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
@ -4807,7 +4911,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
/* I2C Acknowledge failure error interrupt occurred ------------------------*/
if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
{
tmp1 = hi2c->Mode;
tmp1 = CurrentMode;
tmp2 = hi2c->XferCount;
tmp3 = hi2c->State;
tmp4 = hi2c->PreviousState;
@ -4825,7 +4929,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
error |= HAL_I2C_ERROR_AF;
/* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
if (hi2c->Mode == HAL_I2C_MODE_MASTER)
if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
{
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
@ -5150,59 +5254,7 @@ static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
{
if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
if (hi2c->EventCount == 0U)
{
/* If Memory address size is 8Bit */
if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
{
/* Send Memory Address */
hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
hi2c->EventCount += 2U;
}
/* If Memory address size is 16Bit */
else
{
/* Send MSB of Memory Address */
hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
hi2c->EventCount++;
}
}
else if (hi2c->EventCount == 1U)
{
/* Send LSB of Memory Address */
hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
hi2c->EventCount++;
}
else if (hi2c->EventCount == 2U)
{
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
/* Generate Restart */
hi2c->Instance->CR1 |= I2C_CR1_START;
}
else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
/* Write data to DR */
hi2c->Instance->DR = *hi2c->pBuffPtr;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
/* Update counter */
hi2c->XferCount--;
}
else
{
/* Do nothing */
}
}
else
{
/* Do nothing */
}
I2C_MemoryTransmit_TXE_BTF(hi2c);
}
else
{
@ -5274,18 +5326,6 @@ static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
if (hi2c->Mode == HAL_I2C_MODE_MEM)
{
hi2c->Mode = HAL_I2C_MODE_NONE;
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->MemTxCpltCallback(hi2c);
#else
HAL_I2C_MemTxCpltCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
hi2c->Mode = HAL_I2C_MODE_NONE;
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
@ -5296,6 +5336,93 @@ static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
}
}
}
else
{
/* Do nothing */
}
}
/**
* @brief Handle TXE and BTF flag for Memory transmitter
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval None
*/
static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c)
{
/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
HAL_I2C_StateTypeDef CurrentState = hi2c->State;
if (hi2c->EventCount == 0U)
{
/* If Memory address size is 8Bit */
if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
{
/* Send Memory Address */
hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
hi2c->EventCount += 2U;
}
/* If Memory address size is 16Bit */
else
{
/* Send MSB of Memory Address */
hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
hi2c->EventCount++;
}
}
else if (hi2c->EventCount == 1U)
{
/* Send LSB of Memory Address */
hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
hi2c->EventCount++;
}
else if (hi2c->EventCount == 2U)
{
if (CurrentState == HAL_I2C_STATE_BUSY_RX)
{
/* Generate Restart */
hi2c->Instance->CR1 |= I2C_CR1_START;
}
else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
{
/* Write data to DR */
hi2c->Instance->DR = *hi2c->pBuffPtr;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
/* Update counter */
hi2c->XferCount--;
}
else if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
{
/* Generate Stop condition then Call TxCpltCallback() */
/* Disable EVT, BUF and ERR interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
/* Generate Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->MemTxCpltCallback(hi2c);
#else
HAL_I2C_MemTxCpltCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
/* Do nothing */
}
}
else
{
/* Do nothing */
}
}
@ -5332,6 +5459,8 @@ static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
}
}
else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U)))
{
if (I2C_WaitOnSTOPRequestThroughIT(hi2c) == HAL_OK)
{
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
@ -5370,6 +5499,31 @@ static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
hi2c->MasterRxCpltCallback(hi2c);
#else
HAL_I2C_MasterRxCpltCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
else
{
/* Disable EVT, BUF and ERR interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
/* Read data from DR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
/* Update counter */
hi2c->XferCount--;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Call user error callback */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->ErrorCallback(hi2c);
#else
HAL_I2C_ErrorCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
@ -5540,15 +5694,13 @@ static void I2C_Master_SB(I2C_HandleTypeDef *hi2c)
hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
}
if ((hi2c->hdmatx != NULL) || (hi2c->hdmarx != NULL))
{
if ((hi2c->hdmatx->XferCpltCallback != NULL) || (hi2c->hdmarx->XferCpltCallback != NULL))
if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL))
|| ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL)))
{
/* Enable DMA Request */
SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
}
}
}
else
{
if (hi2c->EventCount == 0U)
@ -6159,8 +6311,10 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c)
{
/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
HAL_I2C_StateTypeDef CurrentState = hi2c->State;
HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
uint32_t CurrentError;
if ((hi2c->Mode == HAL_I2C_MODE_MASTER) && (CurrentState == HAL_I2C_STATE_BUSY_RX))
if (((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) && (CurrentState == HAL_I2C_STATE_BUSY_RX))
{
/* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
hi2c->Instance->CR1 &= ~I2C_CR1_POS;
@ -6179,9 +6333,9 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c)
if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT))
{
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
}
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->Mode = HAL_I2C_MODE_NONE;
}
/* Abort DMA transfer */
@ -6278,15 +6432,24 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c)
HAL_I2C_ErrorCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
/* STOP Flag is not set after a NACK reception */
/* STOP Flag is not set after a NACK reception, BusError, ArbitrationLost, OverRun */
CurrentError = hi2c->ErrorCode;
if (((CurrentError & HAL_I2C_ERROR_BERR) == HAL_I2C_ERROR_BERR) || \
((CurrentError & HAL_I2C_ERROR_ARLO) == HAL_I2C_ERROR_ARLO) || \
((CurrentError & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) || \
((CurrentError & HAL_I2C_ERROR_OVR) == HAL_I2C_ERROR_OVR))
{
/* Disable EVT, BUF and ERR interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
}
/* So may inform upper layer that listen phase is stopped */
/* during NACK error treatment */
CurrentState = hi2c->State;
if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN))
{
/* Disable EVT, BUF and ERR interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
@ -6334,7 +6497,11 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
{
hi2c->ErrorCode = HAL_I2C_WRONG_START;
}
return HAL_TIMEOUT;
}
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
@ -6403,7 +6570,11 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
{
hi2c->ErrorCode = HAL_I2C_WRONG_START;
}
return HAL_TIMEOUT;
}
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
@ -6440,7 +6611,11 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
{
hi2c->ErrorCode = HAL_I2C_WRONG_START;
}
return HAL_TIMEOUT;
}
/* Send header of slave address */
@ -6476,7 +6651,11 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
{
hi2c->ErrorCode = HAL_I2C_WRONG_START;
}
return HAL_TIMEOUT;
}
/* Send slave address */
@ -6555,7 +6734,11 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
{
hi2c->ErrorCode = HAL_I2C_WRONG_START;
}
return HAL_TIMEOUT;
}
/* Send slave address */
@ -6625,7 +6808,11 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
/* Wait until SB flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
{
hi2c->ErrorCode = HAL_I2C_WRONG_START;
}
return HAL_TIMEOUT;
}
/* Send slave address */
@ -6658,8 +6845,14 @@ static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
/* Clear Complete callback */
if (hi2c->hdmatx != NULL)
{
hi2c->hdmatx->XferCpltCallback = NULL;
}
if (hi2c->hdmarx != NULL)
{
hi2c->hdmarx->XferCpltCallback = NULL;
}
if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
{
@ -6782,8 +6975,14 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
/* Clear Complete callback */
if (hi2c->hdmatx != NULL)
{
hi2c->hdmatx->XferCpltCallback = NULL;
}
if (hi2c->hdmarx != NULL)
{
hi2c->hdmarx->XferCpltCallback = NULL;
}
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
@ -6808,14 +7007,35 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
*/
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
{
__IO uint32_t count = 0U;
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
HAL_I2C_StateTypeDef CurrentState = hi2c->State;
/* During abort treatment, check that there is no pending STOP request */
/* Wait until STOP flag is reset */
count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U);
do
{
if (count == 0U)
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
break;
}
count--;
}
while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP);
/* Clear Complete callback */
if (hi2c->hdmatx != NULL)
{
hi2c->hdmatx->XferCpltCallback = NULL;
}
if (hi2c->hdmarx != NULL)
{
hi2c->hdmarx->XferCpltCallback = NULL;
}
/* Disable Acknowledge */
CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
@ -6823,8 +7043,14 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
hi2c->XferCount = 0U;
/* Reset XferAbortCallback */
if (hi2c->hdmatx != NULL)
{
hi2c->hdmatx->XferAbortCallback = NULL;
}
if (hi2c->hdmarx != NULL)
{
hi2c->hdmarx->XferAbortCallback = NULL;
}
/* Disable I2C peripheral to prevent dummy data in buffer */
__HAL_I2C_DISABLE(hi2c);
@ -7070,6 +7296,33 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
return HAL_OK;
}
/**
* @brief This function handles I2C Communication Timeout for specific usage of STOP request through Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c)
{
__IO uint32_t count = 0U;
/* Wait until STOP flag is reset */
count = I2C_TIMEOUT_STOP_FLAG * (SystemCoreClock / 25U / 1000U);
do
{
count--;
if (count == 0U)
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
return HAL_ERROR;
}
}
while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP);
return HAL_OK;
}
/**
* @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains

60
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c
View File

@ -16,8 +16,8 @@
(+) The IWDG can be started by either software or hardware (configurable
through option byte).
(+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
if the main clock fails.
(+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
active even if the main clock fails.
(+) Once the IWDG is started, the LSI is forced ON and both cannot be
disabled. The counter starts counting down from the reset value (0xFFF).
@ -25,36 +25,47 @@
generated (IWDG reset).
(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
the IWDG_RLR value is reloaded in the counter and the watchdog reset is
prevented.
the IWDG_RLR value is reloaded into the counter and the watchdog reset
is prevented.
(+) The IWDG is implemented in the VDD voltage domain that is still functional
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
reset occurs.
(+) Debug mode: When the microcontroller enters debug mode (core halted),
the IWDG counter either continues to work normally or stops, depending
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
[..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
The IWDG timeout may vary due to LSI frequency dispersion. STM32F1xx
devices provide the capability to measure the LSI frequency (LSI clock
connected internally to TIM5 CH4 input capture). The measured value
can be used to have an IWDG timeout with an acceptable accuracy.
The IWDG timeout may vary due to LSI clock frequency dispersion.
STM32F1xx devices provide the capability to measure the LSI clock
frequency (LSI clock is internally connected to TIM5 CH4 input capture).
The measured value can be used to have an IWDG timeout with an
acceptable accuracy.
[..] Default timeout value (necessary for IWDG_SR status register update):
Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
This frequency being subject to variations as mentioned above, the
default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
below) may become too short or too long.
In such cases, this default timeout value can be tuned by redefining
the constant LSI_VALUE at user-application level (based, for instance,
on the measured LSI clock frequency as explained above).
##### How to use this driver #####
==============================================================================
[..]
(#) Use IWDG using HAL_IWDG_Init() function to :
(++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
clock is forced ON and IWDG counter starts downcounting.
(++) Enable write access to configuration register: IWDG_PR & IWDG_RLR.
clock is forced ON and IWDG counter starts counting down.
(++) Enable write access to configuration registers:
IWDG_PR and IWDG_RLR.
(++) Configure the IWDG prescaler and counter reload value. This reload
value will be loaded in the IWDG counter each time the watchdog is
reloaded, then the IWDG will start counting down from this value.
(++) wait for status flags to be reset"
(++) Wait for status flags to be reset.
(#) Then the application program must refresh the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
@ -91,7 +102,7 @@
*/
#ifdef HAL_IWDG_MODULE_ENABLED
/** @defgroup IWDG IWDG
/** @addtogroup IWDG
* @brief IWDG HAL module driver.
* @{
*/
@ -101,10 +112,14 @@
/** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{
*/
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
higher prescaler (256), and according to HSI variation, we need to wait at
least 6 cycles so 48 ms. */
#define HAL_IWDG_DEFAULT_TIMEOUT 48U
/* Status register needs up to 5 LSI clock periods divided by the clock
prescaler to be updated. The number of LSI clock periods is upper-rounded to
6 for the timeout value calculation.
The timeout value is also calculated using the highest prescaler (256) and
the LSI_VALUE constant. The value of this constant can be changed by the user
to take into account possible LSI clock period variations.
The timeout value is multiplied by 1000 to be converted in milliseconds. */
#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE)
/**
* @}
*/
@ -158,10 +173,11 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
/* Enable IWDG. LSI is turned on automaticaly */
/* Enable IWDG. LSI is turned on automatically */
__HAL_IWDG_START(hiwdg);
/* Enable write access to IWDG_PR and IWDG_RLR registers by writing 0x5555 in KR */
/* Enable write access to IWDG_PR and IWDG_RLR registers by writing
0x5555 in KR */
IWDG_ENABLE_WRITE_ACCESS(hiwdg);
/* Write to IWDG registers the Prescaler & Reload values to work with */
@ -172,7 +188,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
tickstart = HAL_GetTick();
/* Wait for register to be updated */
while (hiwdg->Instance->SR != RESET)
while (hiwdg->Instance->SR != 0x00u)
{
if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
{
@ -191,6 +207,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
* @}
*/
/** @addtogroup IWDG_Exported_Functions_Group2
* @brief IO operation functions
*
@ -205,6 +222,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
* @{
*/
/**
* @brief Refresh the IWDG.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains

10
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c
View File

@ -135,10 +135,8 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
uint16_t ep_addr,
uint16_t ep_kind,
uint32_t pmaadress)
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
uint16_t ep_kind, uint32_t pmaadress)
{
PCD_EPTypeDef *ep;
@ -176,8 +174,8 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
* @brief Software Device Connection,
* this function is not required by USB OTG FS peripheral, it is used
* only by USB Device FS peripheral.
* @param hpcd: PCD handle
* @param state: connection state (0 : disconnected / 1: connected)
* @param hpcd PCD handle
* @param state connection state (0 : disconnected / 1: connected)
* @retval None
*/
__weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)

1038
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c
View File

File diff suppressed because it is too large Load Diff

457
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c
View File

@ -54,7 +54,7 @@
the commutation event).
(#) Activate the TIM peripheral using one of the start functions:
(++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
(++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
(++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
(++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
(++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
@ -90,9 +90,11 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
/* Exported functions --------------------------------------------------------*/
@ -123,6 +125,9 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha
*/
/**
* @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
* @note When the timer instance is initialized in Hall Sensor Interface mode,
* timer channels 1 and channel 2 are reserved and cannot be used for
* other purpose.
* @param htim TIM Hall Sensor Interface handle
* @param sConfig TIM Hall Sensor configuration structure
* @retval HAL status
@ -208,6 +213,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen
htim->Instance->CR2 &= ~TIM_CR2_MMS;
htim->Instance->CR2 |= TIM_TRGO_OC2REF;
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
@ -241,6 +255,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
HAL_TIMEx_HallSensor_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/* Change the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
/* Change the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@ -288,20 +311,46 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
{
uint32_t tmpsmcr;
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
/* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
/* Set the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the Input Capture channel 1
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
{
__HAL_TIM_ENABLE(htim);
}
}
else
{
__HAL_TIM_ENABLE(htim);
}
/* Return function status */
return HAL_OK;
@ -324,6 +373,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -336,10 +391,29 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
{
uint32_t tmpsmcr;
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
/* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
/* Set the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the capture compare Interrupts 1 event */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
@ -348,11 +422,18 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
{
__HAL_TIM_ENABLE(htim);
}
}
else
{
__HAL_TIM_ENABLE(htim);
}
/* Return function status */
return HAL_OK;
@ -378,6 +459,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -392,29 +479,36 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
{
uint32_t tmpsmcr;
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
/* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
if (htim->State == HAL_TIM_STATE_BUSY)
/* Set the TIM channel state */
if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
|| (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if (htim->State == HAL_TIM_STATE_READY)
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
&& (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
if (((uint32_t)pData == 0U) && (Length > 0U))
if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
else
{
htim->State = HAL_TIM_STATE_BUSY;
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
/* nothing to do */
return HAL_ERROR;
}
/* Enable the Input Capture channel 1
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
@ -428,17 +522,25 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
/* Enable the DMA channel for Capture 1*/
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
/* Enable the capture compare 1 Interrupt */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
{
__HAL_TIM_ENABLE(htim);
}
}
else
{
__HAL_TIM_ENABLE(htim);
}
/* Return function status */
return HAL_OK;
@ -463,9 +565,14 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
(void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -512,6 +619,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
/* Check the TIM complementary channel state */
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
{
return HAL_ERROR;
}
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
@ -519,11 +635,18 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
{
__HAL_TIM_ENABLE(htim);
}
}
else
{
__HAL_TIM_ENABLE(htim);
}
/* Return function status */
return HAL_OK;
@ -554,6 +677,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -576,6 +702,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
/* Check the TIM complementary channel state */
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
{
return HAL_ERROR;
}
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
switch (Channel)
{
case TIM_CHANNEL_1:
@ -614,11 +749,18 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
{
__HAL_TIM_ENABLE(htim);
}
}
else
{
__HAL_TIM_ENABLE(htim);
}
/* Return function status */
return HAL_OK;
@ -684,6 +826,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -708,24 +853,25 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
if (htim->State == HAL_TIM_STATE_BUSY)
/* Set the TIM complementary channel state */
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
{
return HAL_BUSY;
}
else if (htim->State == HAL_TIM_STATE_READY)
else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
if (((uint32_t)pData == 0U) && (Length > 0U))
if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
else
{
htim->State = HAL_TIM_STATE_BUSY;
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
/* nothing to do */
return HAL_ERROR;
}
switch (Channel)
@ -733,15 +879,16 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
case TIM_CHANNEL_1:
{
/* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@ -752,15 +899,16 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
case TIM_CHANNEL_2:
{
/* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@ -771,15 +919,16 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
case TIM_CHANNEL_3:
{
/* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@ -798,11 +947,18 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
{
__HAL_TIM_ENABLE(htim);
}
}
else
{
__HAL_TIM_ENABLE(htim);
}
/* Return function status */
return HAL_OK;
@ -863,8 +1019,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@ -921,6 +1077,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
/* Check the TIM complementary channel state */
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
{
return HAL_ERROR;
}
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
@ -928,11 +1093,18 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
{
__HAL_TIM_ENABLE(htim);
}
}
else
{
__HAL_TIM_ENABLE(htim);
}
/* Return function status */
return HAL_OK;
@ -962,6 +1134,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -984,6 +1159,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
/* Check the TIM complementary channel state */
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
{
return HAL_ERROR;
}
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
switch (Channel)
{
case TIM_CHANNEL_1:
@ -1021,11 +1205,18 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
{
__HAL_TIM_ENABLE(htim);
}
}
else
{
__HAL_TIM_ENABLE(htim);
}
/* Return function status */
return HAL_OK;
@ -1092,6 +1283,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -1116,39 +1310,42 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
if (htim->State == HAL_TIM_STATE_BUSY)
/* Set the TIM complementary channel state */
if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
{
return HAL_BUSY;
}
else if (htim->State == HAL_TIM_STATE_READY)
else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
if (((uint32_t)pData == 0U) && (Length > 0U))
if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
else
{
htim->State = HAL_TIM_STATE_BUSY;
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
}
}
else
{
/* nothing to do */
return HAL_ERROR;
}
switch (Channel)
{
case TIM_CHANNEL_1:
{
/* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 1 DMA request */
@ -1159,15 +1356,16 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
case TIM_CHANNEL_2:
{
/* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 2 DMA request */
@ -1178,15 +1376,16 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
case TIM_CHANNEL_3:
{
/* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 3 DMA request */
@ -1205,11 +1404,18 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
{
__HAL_TIM_ENABLE(htim);
}
}
else
{
__HAL_TIM_ENABLE(htim);
}
/* Return function status */
return HAL_OK;
@ -1270,8 +1476,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@ -1311,11 +1517,27 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);
HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Enable the complementary One Pulse output */
/* Check the TIM channels state */
if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
|| (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
/* Set the TIM channels state */
TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
@ -1336,12 +1558,14 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Disable the complementary One Pulse output */
/* Disable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@ -1349,6 +1573,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM channels state */
TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -1365,17 +1593,33 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);
HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Check the TIM channels state */
if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
|| (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
/* Set the TIM channels state */
TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
/* Enable the complementary One Pulse output */
/* Enable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
/* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
@ -1396,6 +1640,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
@ -1405,8 +1651,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
/* Disable the complementary One Pulse output */
/* Disable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
/* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
@ -1414,6 +1661,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Set the TIM channels state */
TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
}
@ -1633,7 +1884,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
uint32_t tmpsmcr;
/* Check the parameters */
assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
@ -1654,16 +1905,19 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
@ -1733,6 +1987,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
*/
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
UNUSED(Remap);
return HAL_OK;
}
@ -1829,6 +2086,27 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
return htim->State;
}
/**
* @brief Return actual state of the TIM complementary channel.
* @param htim TIM handle
* @param ChannelN TIM Complementary channel
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1
* @arg TIM_CHANNEL_2: TIM Channel 2
* @arg TIM_CHANNEL_3: TIM Channel 3
* @retval TIM Complementary channel state
*/
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN)
{
HAL_TIM_ChannelStateTypeDef channel_state;
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
return channel_state;
}
/**
* @}
*/
@ -1881,6 +2159,103 @@ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
}
/**
* @brief TIM DMA Delay Pulse complete callback (complementary channel).
* @param hdma pointer to DMA handle.
* @retval None
*/
static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
}
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
}
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
}
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
}
}
else
{
/* nothing to do */
}
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_PWM_PulseFinishedCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
/**
* @brief TIM DMA error callback (complementary channel)
* @param hdma pointer to DMA handle.
* @retval None
*/
static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
}
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
}
else
{
/* nothing to do */
}
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->ErrorCallback(htim);
#else
HAL_TIM_ErrorCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
/**
* @brief Enables or disables the TIM Capture Compare Channel xN.
* @param TIMx to select the TIM peripheral

227
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c
View File

@ -1026,7 +1026,8 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint16_t *tmp;
uint8_t *pdata8bits;
uint16_t *pdata16bits;
uint32_t tickstart = 0U;
/* Check that a Tx process is not already ongoing */
@ -1048,34 +1049,39 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
huart->TxXferSize = Size;
huart->TxXferCount = Size;
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
pdata8bits = NULL;
pdata16bits = (uint16_t *) pData;
}
else
{
pdata8bits = pData;
pdata16bits = NULL;
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
while (huart->TxXferCount > 0U)
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
if (pdata8bits == NULL)
{
huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);
pdata16bits++;
}
else
{
huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);
pdata8bits++;
}
huart->TxXferCount--;
if (huart->Init.WordLength == UART_WORDLENGTH_9B)
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
tmp = (uint16_t *) pData;
huart->Instance->DR = (*tmp & (uint16_t)0x01FF);
if (huart->Init.Parity == UART_PARITY_NONE)
{
pData += 2U;
}
else
{
pData += 1U;
}
}
else
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
huart->Instance->DR = (*pData++ & (uint8_t)0xFF);
}
}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
@ -1086,9 +1092,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
}
else
@ -1111,7 +1114,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
*/
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint16_t *tmp;
uint8_t *pdata8bits;
uint16_t *pdata16bits;
uint32_t tickstart = 0U;
/* Check that a Rx process is not already ongoing */
@ -1134,53 +1138,51 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
huart->RxXferSize = Size;
huart->RxXferCount = Size;
/* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
pdata8bits = NULL;
pdata16bits = (uint16_t *) pData;
}
else
{
pdata8bits = pData;
pdata16bits = NULL;
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
/* Check the remain data to be received */
while (huart->RxXferCount > 0U)
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
if (pdata8bits == NULL)
{
*pdata16bits = (uint16_t)(huart->Instance->DR & 0x01FF);
pdata16bits++;
}
else
{
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
}
else
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
}
pdata8bits++;
}
huart->RxXferCount--;
if (huart->Init.WordLength == UART_WORDLENGTH_9B)
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
tmp = (uint16_t *) pData;
if (huart->Init.Parity == UART_PARITY_NONE)
{
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
pData += 2U;
}
else
{
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
pData += 1U;
}
}
else
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
if (huart->Init.Parity == UART_PARITY_NONE)
{
*pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
}
else
{
*pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
}
}
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
}
else
@ -2060,7 +2062,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
}
/* UART Over-Run interrupt occurred --------------------------------------*/
if (((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
{
huart->ErrorCode |= HAL_UART_ERROR_ORE;
}
@ -2924,20 +2926,13 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
/* Check that a Tx process is ongoing */
if (huart->gState == HAL_UART_STATE_BUSY_TX)
{
if (huart->Init.WordLength == UART_WORDLENGTH_9B)
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
tmp = (uint16_t *) huart->pTxBuffPtr;
huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
if (huart->Init.Parity == UART_PARITY_NONE)
{
huart->pTxBuffPtr += 2U;
}
else
{
huart->pTxBuffPtr += 1U;
}
}
else
{
huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
}
@ -2991,36 +2986,34 @@ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
*/
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
{
uint16_t *tmp;
uint8_t *pdata8bits;
uint16_t *pdata16bits;
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
{
if (huart->Init.WordLength == UART_WORDLENGTH_9B)
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
tmp = (uint16_t *) huart->pRxBuffPtr;
if (huart->Init.Parity == UART_PARITY_NONE)
{
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
pdata8bits = NULL;
pdata16bits = (uint16_t *) huart->pRxBuffPtr;
*pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
huart->pRxBuffPtr += 2U;
}
else
{
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
pdata8bits = (uint8_t *) huart->pRxBuffPtr;
pdata16bits = NULL;
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
}
else
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
}
huart->pRxBuffPtr += 1U;
}
}
else
{
if (huart->Init.Parity == UART_PARITY_NONE)
{
*huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
}
else
{
*huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
}
}
if (--huart->RxXferCount == 0U)
{
@ -3099,48 +3092,28 @@ static void UART_SetConfig(UART_HandleTypeDef *huart)
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
if(huart->Instance == USART1)
{
pclk = HAL_RCC_GetPCLK2Freq();
}
else
{
pclk = HAL_RCC_GetPCLK1Freq();
}
/*-------------------------- USART BRR Configuration ---------------------*/
#if defined(USART_CR1_OVER8)
/* Check the Over Sampling */
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
{
/*-------------------------- USART BRR Configuration ---------------------*/
if(huart->Instance == USART1)
{
pclk = HAL_RCC_GetPCLK2Freq();
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
}
else
{
pclk = HAL_RCC_GetPCLK1Freq();
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
}
}
else
{
/*-------------------------- USART BRR Configuration ---------------------*/
if(huart->Instance == USART1)
{
pclk = HAL_RCC_GetPCLK2Freq();
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
else
{
pclk = HAL_RCC_GetPCLK1Freq();
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
}
#else
/*-------------------------- USART BRR Configuration ---------------------*/
if(huart->Instance == USART1)
{
pclk = HAL_RCC_GetPCLK2Freq();
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
else
{
pclk = HAL_RCC_GetPCLK1Freq();
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
#endif /* USART_CR1_OVER8 */
}

434
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c
View File

@ -104,7 +104,7 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
/* Select FS Embedded PHY */
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
/* Reset after a PHY select and set Host mode */
/* Reset after a PHY select */
ret = USB_CoreReset(USBx);
/* Activate the USB Transceiver */
@ -219,13 +219,12 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
}
/**
* @brief USB_SetCurrentMode : Set functional mode
* @brief USB_SetCurrentMode Set functional mode
* @param USBx Selected device
* @param mode current core mode
* This parameter can be one of these values:
* @arg USB_DEVICE_MODE: Peripheral mode
* @arg USB_HOST_MODE: Host mode
* @arg USB_DRD_MODE: Dual Role Device mode
* @arg USB_DEVICE_MODE Peripheral mode
* @arg USB_HOST_MODE Host mode
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode)
@ -250,7 +249,7 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDe
}
/**
* @brief USB_DevInit : Initializes the USB_OTG controller registers
* @brief USB_DevInit Initializes the USB_OTG controller registers
* for device mode
* @param USBx Selected device
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
@ -390,8 +389,7 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
{
return HAL_TIMEOUT;
}
}
while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
return HAL_OK;
}
@ -413,8 +411,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
{
return HAL_TIMEOUT;
}
}
while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
return HAL_OK;
}
@ -553,6 +550,12 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP
/* Read DEPCTLn register */
if (ep->is_in == 1U)
{
if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
{
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
}
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |
@ -563,6 +566,12 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP
}
else
{
if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
{
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
}
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |
@ -588,11 +597,23 @@ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, U
/* Read DEPCTLn register */
if (ep->is_in == 1U)
{
if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
{
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;
}
USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));
}
else
{
if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
{
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;
}
USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));
}
@ -785,7 +806,8 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe
* @param len Number of bytes to write
* @retval HAL status
*/
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len)
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
uint8_t ch_ep_num, uint16_t len)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t *pSrc = (uint32_t *)src;
@ -942,7 +964,7 @@ HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t addres
}
/**
* @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
* @brief USB_DevConnect : Connect the USB device by enabling Rpu
* @param USBx Selected device
* @retval HAL status
*/
@ -950,14 +972,16 @@ HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
/* In case phy is stopped, ensure to ungate and restore the phy CLK */
USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
HAL_Delay(3U);
return HAL_OK;
}
/**
* @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
* @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu
* @param USBx Selected device
* @retval HAL status
*/
@ -965,8 +989,10 @@ HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
/* In case phy is stopped, ensure to ungate and restore the phy CLK */
USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
HAL_Delay(3U);
return HAL_OK;
}
@ -1059,7 +1085,7 @@ uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
/**
* @brief USB_ClearInterrupts: clear a USB interrupt
* @param USBx Selected device
* @param interrupt interrupt flag
* @param interrupt flag
* @retval None
*/
void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
@ -1141,8 +1167,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
{
return HAL_TIMEOUT;
}
}
while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
/* Core Soft Reset */
count = 0U;
@ -1154,8 +1179,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
{
return HAL_TIMEOUT;
}
}
while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
return HAL_OK;
}
@ -1282,8 +1306,8 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
* @brief USB_DriveVbus : activate or de-activate vbus
* @param state VBUS state
* This parameter can be one of these values:
* 0 : VBUS Active
* 1 : VBUS Inactive
* 0 : Deactivate VBUS
* 1 : Activate VBUS
* @retval HAL status
*/
HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)
@ -1359,13 +1383,9 @@ uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx)
* This parameter can be a value from 0 to32K
* @retval HAL state
*/
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
uint8_t ch_num,
uint8_t epnum,
uint8_t dev_address,
uint8_t speed,
uint8_t ep_type,
uint16_t mps)
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
uint8_t epnum, uint8_t dev_address, uint8_t speed,
uint8_t ep_type, uint16_t mps)
{
HAL_StatusTypeDef ret = HAL_OK;
uint32_t USBx_BASE = (uint32_t)USBx;
@ -1607,8 +1627,7 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
{
break;
}
}
while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
} while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
}
else
{
@ -1630,8 +1649,7 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
{
break;
}
}
while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
} while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
}
else
{
@ -1711,8 +1729,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
{
break;
}
}
while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
} while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
}
/* Clear any pending Host interrupts */
@ -1761,8 +1778,8 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
#if defined (USB)
/**
* @brief Initializes the USB Core
* @param USBx: USB Instance
* @param cfg : pointer to a USB_CfgTypeDef structure that contains
* @param USBx USB Instance
* @param cfg pointer to a USB_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
@ -1783,12 +1800,15 @@ HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
/**
* @brief USB_EnableGlobalInt
* Enables the controller's Global Int in the AHB Config reg
* @param USBx : Selected device
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
{
uint16_t winterruptmask;
uint32_t winterruptmask;
/* Clear pending interrupts */
USBx->ISTR = 0U;
/* Set winterruptmask variable */
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
@ -1797,7 +1817,7 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
USB_CNTR_RESETM;
/* Set interrupt mask */
USBx->CNTR |= winterruptmask;
USBx->CNTR = (uint16_t)winterruptmask;
return HAL_OK;
}
@ -1805,12 +1825,12 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
/**
* @brief USB_DisableGlobalInt
* Disable the controller's Global Int in the AHB Config reg
* @param USBx : Selected device
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
{
uint16_t winterruptmask;
uint32_t winterruptmask;
/* Set winterruptmask variable */
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
@ -1819,17 +1839,17 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
USB_CNTR_RESETM;
/* Clear interrupt mask */
USBx->CNTR &= ~winterruptmask;
USBx->CNTR &= (uint16_t)(~winterruptmask);
return HAL_OK;
}
/**
* @brief USB_SetCurrentMode : Set functional mode
* @param USBx : Selected device
* @param mode : current core mode
* @brief USB_SetCurrentMode Set functional mode
* @param USBx Selected device
* @param mode current core mode
* This parameter can be one of the these values:
* @arg USB_DEVICE_MODE: Peripheral mode mode
* @arg USB_DEVICE_MODE Peripheral mode
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)
@ -1846,10 +1866,10 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)
}
/**
* @brief USB_DevInit : Initializes the USB controller registers
* @brief USB_DevInit Initializes the USB controller registers
* for device mode
* @param USBx : Selected device
* @param cfg : pointer to a USB_CfgTypeDef structure that contains
* @param USBx Selected device
* @param cfg pointer to a USB_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
@ -1860,41 +1880,17 @@ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
/* Init Device */
/* CNTR_FRES = 1 */
USBx->CNTR = USB_CNTR_FRES;
USBx->CNTR = (uint16_t)USB_CNTR_FRES;
/* CNTR_FRES = 0 */
USBx->CNTR = 0;
USBx->CNTR = 0U;
/* Clear pending interrupts */
USBx->ISTR = 0;
USBx->ISTR = 0U;
/*Set Btable Address*/
USBx->BTABLE = BTABLE_ADDRESS;
/* Enable USB Device Interrupt mask */
(void)USB_EnableGlobalInt(USBx);
return HAL_OK;
}
/**
* @brief USB_SetDevSpeed :Initializes the device speed
* depending on the PHY type and the enumeration speed of the device.
* @param USBx Selected device
* @param speed device speed
* @retval Hal status
*/
HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
UNUSED(speed);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
}
@ -1940,8 +1936,8 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx)
/**
* @brief Activate and configure an endpoint
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
@ -1975,7 +1971,7 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
break;
}
PCD_SET_ENDPOINT(USBx, ep->num, wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX);
PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX));
PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);
@ -2002,9 +1998,11 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
/*Set the endpoint Receive buffer address */
PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
/*Set the endpoint Receive buffer counter*/
PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
PCD_CLEAR_RX_DTOG(USBx, ep->num);
/* Configure VALID status for the Endpoint*/
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
}
@ -2014,6 +2012,7 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
/* Set the endpoint as double buffered */
PCD_SET_EP_DBUF(USBx, ep->num);
/* Set buffer address for double buffered mode */
PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
@ -2023,9 +2022,6 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
PCD_CLEAR_RX_DTOG(USBx, ep->num);
PCD_CLEAR_TX_DTOG(USBx, ep->num);
/* Reset value of the data toggle bits for the endpoint out */
PCD_TX_DTOG(USBx, ep->num);
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
}
@ -2034,7 +2030,6 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
/* Clear the data toggle bits for the endpoint IN/OUT */
PCD_CLEAR_RX_DTOG(USBx, ep->num);
PCD_CLEAR_TX_DTOG(USBx, ep->num);
PCD_RX_DTOG(USBx, ep->num);
if (ep->type != EP_TYPE_ISOC)
{
@ -2056,8 +2051,8 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
/**
* @brief De-activate and de-initialize an endpoint
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
@ -2067,12 +2062,14 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
if (ep->is_in != 0U)
{
PCD_CLEAR_TX_DTOG(USBx, ep->num);
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
}
else
{
PCD_CLEAR_RX_DTOG(USBx, ep->num);
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
}
@ -2098,6 +2095,7 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
PCD_CLEAR_RX_DTOG(USBx, ep->num);
PCD_CLEAR_TX_DTOG(USBx, ep->num);
PCD_RX_DTOG(USBx, ep->num);
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
@ -2108,15 +2106,16 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
}
/**
* @brief USB_EPStartXfer : setup and starts a transfer over an EP
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @brief USB_EPStartXfer setup and starts a transfer over an EP
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
uint16_t pmabuffer;
uint32_t len;
uint16_t pmabuffer;
uint16_t wEPVal;
/* IN endpoint */
if (ep->is_in == 1U)
@ -2125,12 +2124,10 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
if (ep->xfer_len > ep->maxpacket)
{
len = ep->maxpacket;
ep->xfer_len -= len;
}
else
{
len = ep->xfer_len;
ep->xfer_len = 0U;
}
/* configure and validate Tx endpoint */
@ -2140,6 +2137,93 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
}
else
{
/* double buffer bulk management */
if (ep->type == EP_TYPE_BULK)
{
if (ep->xfer_len_db > ep->maxpacket)
{
/* enable double buffer */
PCD_SET_EP_DBUF(USBx, ep->num);
/* each Time to write in PMA xfer_len_db will */
ep->xfer_len_db -= len;
/* Fill the two first buffer in the Buffer0 & Buffer1 */
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
{
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr1;
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
ep->xfer_buff += len;
if (ep->xfer_len_db > ep->maxpacket)
{
ep->xfer_len_db -= len;
}
else
{
len = ep->xfer_len_db;
ep->xfer_len_db = 0U;
}
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr0;
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
}
else
{
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr0;
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
ep->xfer_buff += len;
if (ep->xfer_len_db > ep->maxpacket)
{
ep->xfer_len_db -= len;
}
else
{
len = ep->xfer_len_db;
ep->xfer_len_db = 0U;
}
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr1;
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
}
}
/* auto Switch to single buffer mode when transfer <Mps no need to manage in double buffer */
else
{
len = ep->xfer_len_db;
/* disable double buffer mode */
PCD_CLEAR_EP_DBUF(USBx, ep->num);
/* Set Tx count with nbre of byte to be transmitted */
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
pmabuffer = ep->pmaaddr0;
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
}
}/* end if bulk double buffer */
/* manage isochronous double buffer IN mode */
else
{
/* Write the data to the USB endpoint */
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
@ -2154,13 +2238,17 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr0;
}
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
PCD_FreeUserBuffer(USBx, ep->num, ep->is_in);
}
}
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
}
else /* OUT endpoint */
{
if (ep->doublebuffer == 0U)
{
/* Multi packet transfer */
if (ep->xfer_len > ep->maxpacket)
@ -2173,18 +2261,52 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
len = ep->xfer_len;
ep->xfer_len = 0U;
}
/* configure and validate Rx endpoint */
if (ep->doublebuffer == 0U)
{
/*Set RX buffer count*/
PCD_SET_EP_RX_CNT(USBx, ep->num, len);
}
else
{
/* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */
/* Set the Double buffer counter */
if (ep->type == EP_TYPE_BULK)
{
PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
/* Coming from ISR */
if (ep->xfer_count != 0U)
{
/* update last value to check if there is blocking state */
wEPVal = PCD_GET_ENDPOINT(USBx, ep->num);
/*Blocking State */
if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
(((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
{
PCD_FreeUserBuffer(USBx, ep->num, 0U);
}
}
}
/* iso out double */
else if (ep->type == EP_TYPE_ISOC)
{
/* Multi packet transfer */
if (ep->xfer_len > ep->maxpacket)
{
len = ep->maxpacket;
ep->xfer_len -= len;
}
else
{
len = ep->xfer_len;
ep->xfer_len = 0U;
}
PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
}
else
{
return HAL_ERROR;
}
}
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
}
@ -2192,54 +2314,11 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
return HAL_OK;
}
/**
* @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
* with the EP/channel
* @param USBx : Selected device
* @param src : pointer to source buffer
* @param ch_ep_num : endpoint or host channel number
* @param len : Number of bytes to write
* @retval HAL status
*/
HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
UNUSED(src);
UNUSED(ch_ep_num);
UNUSED(len);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
}
/**
* @brief USB_ReadPacket : read a packet from the Tx FIFO associated
* with the EP/channel
* @param USBx : Selected device
* @param dest : destination pointer
* @param len : Number of bytes to read
* @retval pointer to destination buffer
*/
void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
UNUSED(dest);
UNUSED(len);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return ((void *)NULL);
}
/**
* @brief USB_EPSetStall : set a stall condition over an EP
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @brief USB_EPSetStall set a stall condition over an EP
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
@ -2257,9 +2336,9 @@ HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
}
/**
* @brief USB_EPClearStall : Clear a stall condition over an EP
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @brief USB_EPClearStall Clear a stall condition over an EP
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
@ -2289,28 +2368,28 @@ HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
}
/**
* @brief USB_StopDevice : Stop the usb device mode
* @param USBx : Selected device
* @brief USB_StopDevice Stop the usb device mode
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx)
{
/* disable all interrupts and force USB reset */
USBx->CNTR = USB_CNTR_FRES;
USBx->CNTR = (uint16_t)USB_CNTR_FRES;
/* clear interrupt status register */
USBx->ISTR = 0;
USBx->ISTR = 0U;
/* switch-off device */
USBx->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN);
USBx->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN);
return HAL_OK;
}
/**
* @brief USB_SetDevAddress : Stop the usb device mode
* @param USBx : Selected device
* @param address : new device address to be assigned
* @brief USB_SetDevAddress Stop the usb device mode
* @param USBx Selected device
* @param address new device address to be assigned
* This parameter can be a value from 0 to 255
* @retval HAL status
*/
@ -2319,21 +2398,22 @@ HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address)
if (address == 0U)
{
/* set device address and enable function */
USBx->DADDR = USB_DADDR_EF;
USBx->DADDR = (uint16_t)USB_DADDR_EF;
}
return HAL_OK;
}
/**
* @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
* @param USBx : Selected device
* @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
@ -2343,14 +2423,15 @@ HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx)
}
/**
* @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
* @param USBx : Selected device
* @brief USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
@ -2360,8 +2441,8 @@ HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx)
}
/**
* @brief USB_ReadInterrupts: return the global USB interrupt status
* @param USBx : Selected device
* @brief USB_ReadInterrupts return the global USB interrupt status
* @param USBx Selected device
* @retval HAL status
*/
uint32_t USB_ReadInterrupts(USB_TypeDef *USBx)
@ -2373,8 +2454,8 @@ uint32_t USB_ReadInterrupts(USB_TypeDef *USBx)
}
/**
* @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
* @param USBx : Selected device
* @brief USB_ReadDevAllOutEpInterrupt return the USB device OUT endpoints interrupt status
* @param USBx Selected device
* @retval HAL status
*/
uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx)
@ -2389,8 +2470,8 @@ uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx)
}
/**
* @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
* @param USBx : Selected device
* @brief USB_ReadDevAllInEpInterrupt return the USB device IN endpoints interrupt status
* @param USBx Selected device
* @retval HAL status
*/
uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx)
@ -2406,8 +2487,8 @@ uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx)
/**
* @brief Returns Device OUT EP Interrupt register
* @param USBx : Selected device
* @param epnum : endpoint number
* @param USBx Selected device
* @param epnum endpoint number
* This parameter can be a value from 0 to 15
* @retval Device OUT EP Interrupt register
*/
@ -2425,8 +2506,8 @@ uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum)
/**
* @brief Returns Device IN EP Interrupt register
* @param USBx : Selected device
* @param epnum : endpoint number
* @param USBx Selected device
* @param epnum endpoint number
* This parameter can be a value from 0 to 15
* @retval Device IN EP Interrupt register
*/
@ -2445,7 +2526,7 @@ uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum)
/**
* @brief USB_ClearInterrupts: clear a USB interrupt
* @param USBx Selected device
* @param interrupt interrupt flag
* @param interrupt flag
* @retval None
*/
void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt)
@ -2484,19 +2565,20 @@ HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup)
*/
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx)
{
USBx->CNTR |= USB_CNTR_RESUME;
USBx->CNTR |= (uint16_t)USB_CNTR_RESUME;
return HAL_OK;
}
/**
* @brief USB_DeActivateRemoteWakeup : de-active remote wakeup signalling
* @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx)
{
USBx->CNTR &= ~(USB_CNTR_RESUME);
USBx->CNTR &= (uint16_t)(~USB_CNTR_RESUME);
return HAL_OK;
}
@ -2505,7 +2587,7 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx)
* @param USBx USB peripheral instance register address.
* @param pbUsrBuf pointer to user memory area.
* @param wPMABufAddr address into PMA.
* @param wNBytes: no. of bytes to be copied.
* @param wNBytes no. of bytes to be copied.
* @retval None
*/
void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
@ -2535,11 +2617,11 @@ void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui
}
/**
* @brief Copy a buffer from user memory area to packet memory area (PMA)
* @param USBx: USB peripheral instance register address.
* @brief Copy data from packet memory area (PMA) to user memory buffer
* @param USBx USB peripheral instance register address.
* @param pbUsrBuf pointer to user memory area.
* @param wPMABufAddr address into PMA.
* @param wNBytes: no. of bytes to be copied.
* @param wNBytes no. of bytes to be copied.
* @retval None
*/
void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)

60
NaviKit_stm32.ioc
View File

@ -32,7 +32,7 @@ ADC1.SamplingTime-6\#ChannelRegularConversion=ADC_SAMPLETIME_239CYCLES_5
ADC1.WatchdogChannel=ADC_CHANNEL_TEMPSENSOR
ADC1.WatchdogMode=ADC_ANALOGWATCHDOG_SINGLE_REG
ADC1.master=1
ARM.CMSIS.5.6.0.CMSISJjCORE=true
ARM.CMSIS.5.6.0.CMSISJjCORE_Checked=false
ARM.CMSIS.5.6.0.CMSISJjDSP=Library
ARM.CMSIS.5.6.0.CMSISJjNNOoLib=true
ARM.CMSIS.5.6.0.CMSISOoDriverJjCANJjCustom=true
@ -53,8 +53,8 @@ ARM.CMSIS.5.6.0.CMSISOoDriverJjWiFiJjCustom=true
ARM.CMSIS.5.6.0.DeviceJjIRQOoControllerJjGIC=true
ARM.CMSIS.5.6.0.DeviceJjOSOoTickJjPrivateOoTimer=true
ARM.CMSIS.5.6.0.DeviceJjStartup=COoStartup
ARM.CMSIS.5.6.0.IPParameters=CMSISJjCORE,CMSISJjNNOoLib,DeviceJjIRQOoControllerJjGIC,DeviceJjOSOoTickJjPrivateOoTimer,CMSISOoDriverJjUSARTJjCustom,CMSISOoDriverJjSPIJjCustom,CMSISOoDriverJjSAIJjCustom,CMSISOoDriverJjI2CJjCustom,CMSISOoDriverJjCANJjCustom,CMSISOoDriverJjFlashJjCustom,CMSISOoDriverJjMCIJjCustom,CMSISOoDriverJjNANDJjCustom,CMSISOoDriverJjEthernetJjCustom,CMSISOoDriverJjEthernetOoMACJjCustom,CMSISOoDriverJjEthernetOoPHYJjCustom,CMSISOoDriverJjUSBOoDeviceJjCustom,CMSISOoDriverJjUSBOoHostJjCustom,CMSISOoDriverJjWiFiJjCustom,CMSISJjDSP,DeviceJjStartup
ARM.CMSIS.5.6.0_SwParameter=CMSISOoDriverJjUSARTJjCustom\:true;DeviceJjOSOoTickJjPrivateOoTimer\:true;CMSISOoDriverJjUSBOoDeviceJjCustom\:true;CMSISOoDriverJjCANJjCustom\:true;CMSISJjCORE\:true;CMSISOoDriverJjFlashJjCustom\:true;CMSISOoDriverJjNANDJjCustom\:true;CMSISOoDriverJjEthernetJjCustom\:true;CMSISOoDriverJjEthernetOoMACJjCustom\:true;CMSISOoDriverJjUSBOoHostJjCustom\:true;CMSISOoDriverJjSAIJjCustom\:true;CMSISOoDriverJjWiFiJjCustom\:true;CMSISJjDSP\:Library;CMSISOoDriverJjSPIJjCustom\:true;CMSISOoDriverJjMCIJjCustom\:true;CMSISOoDriverJjEthernetOoPHYJjCustom\:true;DeviceJjIRQOoControllerJjGIC\:true;CMSISJjNNOoLib\:true;DeviceJjStartup\:COoStartup;CMSISOoDriverJjI2CJjCustom\:true;
ARM.CMSIS.5.6.0.IPParameters=CMSISJjNNOoLib,DeviceJjIRQOoControllerJjGIC,DeviceJjOSOoTickJjPrivateOoTimer,CMSISOoDriverJjUSARTJjCustom,CMSISOoDriverJjSPIJjCustom,CMSISOoDriverJjSAIJjCustom,CMSISOoDriverJjI2CJjCustom,CMSISOoDriverJjCANJjCustom,CMSISOoDriverJjFlashJjCustom,CMSISOoDriverJjMCIJjCustom,CMSISOoDriverJjNANDJjCustom,CMSISOoDriverJjEthernetJjCustom,CMSISOoDriverJjEthernetOoMACJjCustom,CMSISOoDriverJjEthernetOoPHYJjCustom,CMSISOoDriverJjUSBOoDeviceJjCustom,CMSISOoDriverJjUSBOoHostJjCustom,CMSISOoDriverJjWiFiJjCustom,CMSISJjDSP,DeviceJjStartup
ARM.CMSIS.5.6.0_SwParameter=CMSISOoDriverJjUSARTJjCustom\:true;DeviceJjOSOoTickJjPrivateOoTimer\:true;CMSISOoDriverJjUSBOoDeviceJjCustom\:true;CMSISOoDriverJjCANJjCustom\:true;CMSISJjCORE\:false;CMSISOoDriverJjFlashJjCustom\:true;CMSISOoDriverJjNANDJjCustom\:true;CMSISOoDriverJjEthernetJjCustom\:true;CMSISOoDriverJjEthernetOoMACJjCustom\:true;CMSISOoDriverJjUSBOoHostJjCustom\:true;CMSISOoDriverJjSAIJjCustom\:true;CMSISOoDriverJjWiFiJjCustom\:true;CMSISJjDSP\:Library;CMSISOoDriverJjSPIJjCustom\:true;CMSISOoDriverJjMCIJjCustom\:true;CMSISOoDriverJjEthernetOoPHYJjCustom\:true;DeviceJjIRQOoControllerJjGIC\:true;CMSISJjNNOoLib\:true;CMSISOoDriverJjI2CJjCustom\:true;
Dma.ADC1.0.Direction=DMA_PERIPH_TO_MEMORY
Dma.ADC1.0.Instance=DMA1_Channel1
Dma.ADC1.0.MemDataAlignment=DMA_MDATAALIGN_WORD
@ -185,8 +185,8 @@ Mcu.ThirdParty0=ARM.CMSIS.5.6.0
Mcu.ThirdPartyNb=1
Mcu.UserConstants=
Mcu.UserName=STM32F107VCTx
MxCube.Version=5.6.1
MxDb.Version=DB.5.0.60
MxCube.Version=6.0.1
MxDb.Version=DB.6.0.0
NVIC.ADC1_2_IRQn=true\:5\:0\:false\:true\:true\:8\:true\:true\:true
NVIC.BusFault_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:false
NVIC.DMA1_Channel1_IRQn=true\:5\:0\:false\:true\:true\:9\:true\:false\:true
@ -201,19 +201,22 @@ NVIC.I2C1_ER_IRQn=true\:5\:0\:true\:true\:true\:7\:true\:true\:true
NVIC.I2C1_EV_IRQn=true\:5\:0\:false\:true\:true\:6\:true\:true\:true
NVIC.MemoryManagement_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.OTG_FS_IRQn=true\:5\:0\:false\:true\:true\:5\:true\:false\:true
NVIC.OTG_FS_IRQn=true\:5\:0\:false\:true\:true\:4\:true\:false\:true
NVIC.PVD_IRQn=true\:5\:0\:true\:true\:true\:1\:true\:true\:true
NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.RCC_IRQn=true\:5\:0\:false\:true\:true\:3\:true\:true\:false
NVIC.RTC_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false
NVIC.SavedPendsvIrqHandlerGenerated=true
NVIC.SavedSvcallIrqHandlerGenerated=true
NVIC.SavedSystickIrqHandlerGenerated=true
NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false
NVIC.TIM1_UP_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.TimeBase=TIM1_UP_IRQn
NVIC.TimeBaseIP=TIM1
NVIC.UART4_IRQn=true\:5\:0\:false\:true\:true\:4\:true\:true\:true
NVIC.USART1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
NVIC.UART4_IRQn=true\:5\:0\:false\:true\:true\:5\:true\:true\:true
NVIC.USART1_IRQn=true\:5\:0\:false\:true\:true\:10\:true\:true\:true
NVIC.UsageFault_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:false
OSC_IN.Mode=HSE-External-Oscillator
OSC_IN.Signal=RCC_OSC_IN
@ -372,6 +375,44 @@ PC8.GPIOParameters=GPIO_Label
PC8.GPIO_Label=SOC_U2_HUB_PWR_STA
PC8.Locked=true
PC8.Signal=GPXTI8
PCC.Checker=false
PCC.Line=STM32F105/107
PCC.MCU=STM32F107V(B-C)Tx
PCC.PartNumber=STM32F107VCTx
PCC.Seq0=2
PCC.Seq0.Step0.Average_Current=2.9 mA
PCC.Seq0.Step0.CPU_Frequency=4 MHz
PCC.Seq0.Step0.Category=In DS Table
PCC.Seq0.Step0.DMIPS=5.0
PCC.Seq0.Step0.Duration=0.1 ms
PCC.Seq0.Step0.Frequency=8 MHz
PCC.Seq0.Step0.Memory=FLASH
PCC.Seq0.Step0.Mode=RUN
PCC.Seq0.Step0.Oscillator=HSE
PCC.Seq0.Step0.Peripherals=
PCC.Seq0.Step0.TaMax=104.56
PCC.Seq0.Step0.User's_Consumption=0 mA
PCC.Seq0.Step0.Vcore=No Scale
PCC.Seq0.Step0.Vdd=3.3
PCC.Seq0.Step0.Voltage_Source=Battery
PCC.Seq0.Step1.Average_Current=26 \u00B5A
PCC.Seq0.Step1.CPU_Frequency=0 Hz
PCC.Seq0.Step1.Category=In DS Table
PCC.Seq0.Step1.DMIPS=0.0
PCC.Seq0.Step1.Duration=0.9 ms
PCC.Seq0.Step1.Frequency=0 Hz
PCC.Seq0.Step1.Memory=n/a
PCC.Seq0.Step1.Mode=STOP
PCC.Seq0.Step1.Oscillator=Regulator_LP
PCC.Seq0.Step1.Peripherals=
PCC.Seq0.Step1.TaMax=105
PCC.Seq0.Step1.User's_Consumption=0 mA
PCC.Seq0.Step1.Vcore=No Scale
PCC.Seq0.Step1.Vdd=3.3
PCC.Seq0.Step1.Voltage_Source=Battery
PCC.Series=STM32F1
PCC.Temperature=25
PCC.Vdd=3.3
PD0.GPIOParameters=GPIO_Label
PD0.GPIO_Label=SOC_U3_HUB_PWR_CTL
PD0.Locked=true
@ -498,7 +539,7 @@ ProjectManager.CustomerFirmwarePackage=
ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32F107VCTx
ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.8.0
ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.8.3
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x400
@ -511,6 +552,7 @@ ProjectManager.PreviousToolchain=
ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=NaviKit_stm32.ioc
ProjectManager.ProjectName=NaviKit_stm32
ProjectManager.RegisterCallBack=
ProjectManager.StackSize=0x800
ProjectManager.TargetToolchain=STM32CubeIDE
ProjectManager.ToolChainLocation=

9
USB_DEVICE/App/usbd_cdc_if.c
View File

@ -251,10 +251,11 @@ static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length)
* through this function.
*
* @note
* This function will block any OUT packet reception on USB endpoint
* untill exiting this function. If you exit this function before transfer
* is complete on CDC interface (ie. using DMA controller) it will result
* in receiving more data while previous ones are still not sent.
* This function will issue a NAK packet on any OUT packet received on
* USB endpoint until exiting this function. If you exit this function
* before transfer is complete on CDC interface (ie. using DMA controller)
* it will result in receiving more data while previous ones are still
* not sent.
*
* @param Buf: Buffer of data to be received
* @param Len: Number of data received (in bytes)

1
USB_DEVICE/App/usbd_desc.c
View File

@ -108,7 +108,6 @@ static void IntToUnicode(uint32_t value, uint8_t * pbuf, uint8_t len);
* @}
*/
/** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes
* @brief Private functions declaration for FS.
* @{