160 lines
3.9 KiB
C
160 lines
3.9 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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*/
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#ifndef __PMU_H__
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#define __PMU_H__
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#include "board.h"
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/* Number of counters */
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#define ARM_PMU_CNTER_NR 4
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enum rt_hw_pmu_event_type {
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ARM_PMU_EVENT_PMNC_SW_INCR = 0x00,
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ARM_PMU_EVENT_L1_ICACHE_REFILL = 0x01,
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ARM_PMU_EVENT_ITLB_REFILL = 0x02,
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ARM_PMU_EVENT_L1_DCACHE_REFILL = 0x03,
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ARM_PMU_EVENT_L1_DCACHE_ACCESS = 0x04,
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ARM_PMU_EVENT_DTLB_REFILL = 0x05,
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ARM_PMU_EVENT_MEM_READ = 0x06,
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ARM_PMU_EVENT_MEM_WRITE = 0x07,
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ARM_PMU_EVENT_INSTR_EXECUTED = 0x08,
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ARM_PMU_EVENT_EXC_TAKEN = 0x09,
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ARM_PMU_EVENT_EXC_EXECUTED = 0x0A,
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ARM_PMU_EVENT_CID_WRITE = 0x0B,
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};
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/* Enable bit */
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#define ARM_PMU_PMCR_E (0x01 << 0)
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/* Event counter reset */
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#define ARM_PMU_PMCR_P (0x01 << 1)
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/* Cycle counter reset */
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#define ARM_PMU_PMCR_C (0x01 << 2)
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/* Cycle counter divider */
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#define ARM_PMU_PMCR_D (0x01 << 3)
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#ifdef __GNUC__
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rt_inline void rt_hw_pmu_enable_cnt(int divide64)
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{
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unsigned long pmcr;
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unsigned long pmcntenset;
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asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));
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pmcr |= ARM_PMU_PMCR_E | ARM_PMU_PMCR_P | ARM_PMU_PMCR_C;
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if (divide64)
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pmcr |= ARM_PMU_PMCR_D;
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else
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pmcr &= ~ARM_PMU_PMCR_D;
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asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr));
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/* enable all the counters */
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pmcntenset = ~0;
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asm volatile ("mcr p15, 0, %0, c9, c12, 1" :: "r"(pmcntenset));
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/* clear overflows(just in case) */
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asm volatile ("mcr p15, 0, %0, c9, c12, 3" :: "r"(pmcntenset));
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}
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rt_inline unsigned long rt_hw_pmu_get_control(void)
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{
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unsigned long pmcr;
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asm ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));
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return pmcr;
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}
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rt_inline unsigned long rt_hw_pmu_get_ceid(void)
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{
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unsigned long reg;
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/* only PMCEID0 is supported, PMCEID1 is RAZ. */
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asm ("mrc p15, 0, %0, c9, c12, 6" : "=r"(reg));
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return reg;
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}
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rt_inline unsigned long rt_hw_pmu_get_cnten(void)
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{
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unsigned long pmcnt;
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asm ("mrc p15, 0, %0, c9, c12, 1" : "=r"(pmcnt));
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return pmcnt;
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}
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rt_inline void rt_hw_pmu_reset_cycle(void)
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{
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unsigned long pmcr;
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asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));
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pmcr |= ARM_PMU_PMCR_C;
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asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr));
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asm volatile ("isb");
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}
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rt_inline void rt_hw_pmu_reset_event(void)
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{
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unsigned long pmcr;
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asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr));
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pmcr |= ARM_PMU_PMCR_P;
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asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr));
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asm volatile ("isb");
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}
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rt_inline unsigned long rt_hw_pmu_get_cycle(void)
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{
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unsigned long cyc;
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asm volatile ("isb");
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asm volatile ("mrc p15, 0, %0, c9, c13, 0" : "=r"(cyc));
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return cyc;
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}
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rt_inline void rt_hw_pmu_select_counter(int idx)
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{
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RT_ASSERT(idx < ARM_PMU_CNTER_NR);
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asm volatile ("mcr p15, 0, %0, c9, c12, 5" : : "r"(idx));
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/* Linux add an isb here, don't know why here. */
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asm volatile ("isb");
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}
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rt_inline void rt_hw_pmu_select_event(int idx,
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enum rt_hw_pmu_event_type eve)
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{
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RT_ASSERT(idx < ARM_PMU_CNTER_NR);
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rt_hw_pmu_select_counter(idx);
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asm volatile ("mcr p15, 0, %0, c9, c13, 1" : : "r"(eve));
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}
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rt_inline unsigned long rt_hw_pmu_read_counter(int idx)
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{
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unsigned long reg;
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rt_hw_pmu_select_counter(idx);
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asm volatile ("isb");
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asm volatile ("mrc p15, 0, %0, c9, c13, 2" : "=r"(reg));
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return reg;
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}
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rt_inline unsigned long rt_hw_pmu_get_ovsr(void)
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{
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unsigned long reg;
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asm volatile ("isb");
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asm ("mrc p15, 0, %0, c9, c12, 3" : "=r"(reg));
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return reg;
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}
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rt_inline void rt_hw_pmu_clear_ovsr(unsigned long reg)
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{
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asm ("mcr p15, 0, %0, c9, c12, 3" : : "r"(reg));
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asm volatile ("isb");
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}
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#endif
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void rt_hw_pmu_dump_feature(void);
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#endif /* end of include guard: __PMU_H__ */
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