From 0290eb431252c6865ba1aaa09c4779b420012933 Mon Sep 17 00:00:00 2001 From: zhangchengkai Date: Mon, 10 Jan 2022 20:04:48 +0800 Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0usart=E9=A9=B1=E5=8A=A8?= =?UTF-8?q?=EF=BC=8C=E6=94=AF=E6=8C=81lpuart0=E4=BD=9C=E4=B8=BA=E7=B3=BB?= =?UTF-8?q?=E7=BB=9F=E6=97=A5=E5=BF=97=E8=BE=93=E5=87=BA=E7=AB=AF=E5=8F=A3?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .config | 106 +++--- applications/main.c | 10 +- board/Kconfig | 16 + board/board.h | 27 +- board/board_config.h | 49 ++- drivers/drv_usart.c | 312 ++++++++++++++++++ drivers/drv_usart.h | 161 +++++++++ openocd.log | 2 + .../tools/kconfig-frontends/kconfig-mconf | Bin 0 -> 186424 bytes rtconfig.h | 51 +-- 10 files changed, 663 insertions(+), 71 deletions(-) create mode 100644 drivers/drv_usart.c create mode 100644 drivers/drv_usart.h create mode 100644 openocd.log create mode 100755 rt-thread/tools/kconfig-frontends/kconfig-mconf diff --git a/.config b/.config index 2da3f0c..3e0086f 100644 --- a/.config +++ b/.config @@ -7,7 +7,6 @@ # RT-Thread Kernel # CONFIG_RT_NAME_MAX=8 -# CONFIG_RT_USING_BIG_ENDIAN is not set # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=4 @@ -18,7 +17,6 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32 CONFIG_RT_TICK_PER_SECOND=1000 CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y -CONFIG_RT_HOOK_USING_FUNC_PTR=y CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=256 @@ -31,8 +29,7 @@ CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 # # CONFIG_RT_KSERVICE_USING_STDLIB is not set # CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set -# CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_PRINTF_LONGLONG is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set CONFIG_RT_DEBUG=y # CONFIG_RT_DEBUG_COLOR is not set # CONFIG_RT_DEBUG_INIT_CONFIG is not set @@ -60,16 +57,12 @@ CONFIG_RT_USING_MESSAGEQUEUE=y # Memory Management # CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMHEAP is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y -# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set # CONFIG_RT_USING_USERHEAP is not set -# CONFIG_RT_USING_NOHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set CONFIG_RT_USING_HEAP=y # @@ -80,8 +73,9 @@ CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_INTERRUPT_INFO is not set CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" -CONFIG_RT_VER_NUM=0x40100 +CONFIG_RT_CONSOLE_DEVICE_NAME="lpuart0" +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_VER_NUM=0x40005 # CONFIG_RT_USING_CPU_FFS is not set # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set @@ -92,7 +86,6 @@ CONFIG_RT_USING_COMPONENTS_INIT=y CONFIG_RT_USING_USER_MAIN=y CONFIG_RT_MAIN_THREAD_STACK_SIZE=512 CONFIG_RT_MAIN_THREAD_PRIORITY=10 -# CONFIG_RT_USING_LEGACY is not set # # C++ features @@ -127,6 +120,7 @@ CONFIG_FINSH_ARG_MAX=10 # Device Drivers # CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y CONFIG_RT_USING_SERIAL_V1=y @@ -160,35 +154,18 @@ CONFIG_RT_USING_PIN=y # # Using USB # -# CONFIG_RT_USING_USB is not set # CONFIG_RT_USING_USB_HOST is not set # CONFIG_RT_USING_USB_DEVICE is not set # # POSIX layer and C standard library # +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_LIBC_USING_TIME=y # CONFIG_RT_USING_MODULE is not set CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 -# -# POSIX (Portable Operating System Interface) layer -# -# CONFIG_RT_USING_POSIX_FS is not set -# CONFIG_RT_USING_POSIX_DELAY is not set -# CONFIG_RT_USING_POSIX_CLOCK is not set -# CONFIG_RT_USING_PTHREADS is not set - -# -# Interprocess Communication (IPC) -# -# CONFIG_RT_USING_POSIX_PIPE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set - -# -# Socket is in the 'Network' category -# - # # Network # @@ -222,16 +199,35 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # Utilities # # CONFIG_RT_USING_RYM is not set -# CONFIG_RT_USING_ULOG is not set +CONFIG_RT_USING_ULOG=y +# CONFIG_ULOG_OUTPUT_LVL_A is not set +# CONFIG_ULOG_OUTPUT_LVL_E is not set +# CONFIG_ULOG_OUTPUT_LVL_W is not set +# CONFIG_ULOG_OUTPUT_LVL_I is not set +CONFIG_ULOG_OUTPUT_LVL_D=y +CONFIG_ULOG_OUTPUT_LVL=7 +# CONFIG_ULOG_USING_ISR_LOG is not set +CONFIG_ULOG_ASSERT_ENABLE=y +CONFIG_ULOG_LINE_BUF_SIZE=128 +# CONFIG_ULOG_USING_ASYNC_OUTPUT is not set + +# +# log format +# +# CONFIG_ULOG_OUTPUT_FLOAT is not set +CONFIG_ULOG_USING_COLOR=y +CONFIG_ULOG_OUTPUT_TIME=y +# CONFIG_ULOG_TIME_USING_TIMESTAMP is not set +CONFIG_ULOG_OUTPUT_LEVEL=y +CONFIG_ULOG_OUTPUT_TAG=y +# CONFIG_ULOG_OUTPUT_THREAD_NAME is not set +CONFIG_ULOG_BACKEND_USING_CONSOLE=y +# CONFIG_ULOG_USING_FILTER is not set +# CONFIG_ULOG_USING_SYSLOG is not set # CONFIG_RT_USING_UTEST is not set # CONFIG_RT_USING_VAR_EXPORT is not set # CONFIG_RT_USING_RT_LINK is not set -# -# RT-Thread Utestcases -# -# CONFIG_RT_USING_UTESTCASES is not set - # # RT-Thread online packages # @@ -440,7 +436,12 @@ CONFIG_PKG_EASYLOGGER_VER="v2.0.0" # CONFIG_PKG_USING_SEGGER_RTT is not set # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_QRCODE is not set -# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +CONFIG_PKG_USING_ULOG_EASYFLASH=y +CONFIG_PKG_ULOG_EASYFLASH_PATH="/packages/tools/ulog_easyflash" +CONFIG_PKG_USING_ULOG_EASYFLASH_V00200=y +# CONFIG_PKG_USING_ULOG_EASYFLASH_V00100 is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH_LATEST_VERSION is not set +CONFIG_PKG_ULOG_EASYFLASH_VER="v0.2.0" # CONFIG_PKG_USING_ULOG_FILE is not set # CONFIG_PKG_USING_LOGMGR is not set # CONFIG_PKG_USING_ADBD is not set @@ -500,8 +501,21 @@ CONFIG_PKG_EASYLOGGER_VER="v2.0.0" # # CMSIS: ARM Cortex-M Microcontroller Software Interface Standard # -# CONFIG_PKG_USING_CMSIS_5 is not set -# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +CONFIG_PKG_USING_CMSIS_5=y +CONFIG_PKG_CMSIS_5_PATH="/packages/system/CMSIS/CMSIS_5" +CONFIG_PKG_CMSIS_CORE=y +# CONFIG_PKG_CMSIS_NN is not set +# CONFIG_PKG_CMSIS_DSP is not set +CONFIG_PKG_CMSIS_5_AUX_VER="latest" +CONFIG_PKG_USING_CMSIS_5_LATEST_VERSION=y +# CONFIG_PKG_USING_CMSIS_5_V50800 is not set +CONFIG_PKG_CMSIS_5_VER="latest" +CONFIG_PKG_USING_CMSIS_5_AUX=y +CONFIG_PKG_CMSIS_5_AUX_PATH="/packages/system/CMSIS/CMSIS_5_AUX" +CONFIG_PKG_USING_CMSIS_RTOS2=y +CONFIG_PKG_CMSIS_RTOS2_PATH="/packages/system/CMSIS/CMSIS_RTOS2" +CONFIG_PKG_USING_CMSIS_RTOS2_LATEST_VERSION=y +CONFIG_PKG_CMSIS_RTOS2_VER="latest" # # Micrium: Micrium software products porting for RT-Thread @@ -701,7 +715,13 @@ CONFIG_MCU_HC32L073=y # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y -# CONFIG_BSP_USING_UART is not set +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +CONFIG_BSP_USING_LPUART0=y +# CONFIG_BSP_USING_LPUART1 is not set # CONFIG_BSP_USING_I2C1 is not set # diff --git a/applications/main.c b/applications/main.c index 8087b98..6dab9dc 100644 --- a/applications/main.c +++ b/applications/main.c @@ -1,3 +1,10 @@ +/* + * @Description: + * @Date: 2022-01-10 17:05:41 + * @LastEditors: CK.Zh + * @LastEditTime: 2022-01-10 17:27:06 + * @FilePath: /motion_ec_rtt/applications/main.c + */ /* * Copyright (C) 2021, Huada Semiconductor Co., Ltd. * @@ -26,8 +33,7 @@ ******************************************************************************/ /* defined the LED pin: PC9 */ -#define LED_PIN GET_PIN(C, 13) -#define KEY_PIN GET_PIN(B, 9) + /******************************************************************************* * Global variable definitions (declared in header file with 'extern') diff --git a/board/Kconfig b/board/Kconfig index a98d7e2..ced2c45 100644 --- a/board/Kconfig +++ b/board/Kconfig @@ -29,6 +29,22 @@ menu "On-chip Peripheral Drivers" config BSP_USING_UART1 bool "Enable UART1" default n + + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_USING_UART3 + bool "Enable UART3" + default n + + config BSP_USING_LPUART0 + bool "Enable LPUART0" + default n + + config BSP_USING_LPUART1 + bool "Enable LPUART1" + default n endif menuconfig BSP_USING_I2C1 diff --git a/board/board.h b/board/board.h index 49c43ef..f0261b9 100644 --- a/board/board.h +++ b/board/board.h @@ -2,8 +2,8 @@ * @Description: * @Date: 2022-01-06 14:31:32 * @LastEditors: CK.Zh - * @LastEditTime: 2022-01-10 11:24:25 - * @FilePath: /rt-thread/bsp/hc32l073/board/board.h + * @LastEditTime: 2022-01-10 17:27:17 + * @FilePath: /motion_ec_rtt/board/board.h */ /* * Copyright (C) 2021, Huada Semiconductor Co., Ltd. @@ -46,9 +46,32 @@ extern int __bss_end; #define HEAP_END SRAM_END #endif + +#define LED_PIN GET_PIN(C, 13) +#define KEY_PIN GET_PIN(B, 9) +#define KEY_PIN GET_PIN(B, 9) +#define KEY_PIN GET_PIN(B, 9) +#define KEY_PIN GET_PIN(B, 9) +#define KEY_PIN GET_PIN(B, 9) +#define KEY_PIN GET_PIN(B, 9) +#define KEY_PIN GET_PIN(B, 9) +#define KEY_PIN GET_PIN(B, 9) +#define KEY_PIN GET_PIN(B, 9) + + + + + + + + + + void rt_hw_board_init(void); void rt_hw_us_delay(rt_uint32_t us); + + #endif // <<< Use Configuration Wizard in Context Menu >>> diff --git a/board/board_config.h b/board/board_config.h index 3ac3199..5c61336 100644 --- a/board/board_config.h +++ b/board/board_config.h @@ -2,8 +2,8 @@ * @Description: * @Date: 2022-01-06 14:27:36 * @LastEditors: CK.Zh - * @LastEditTime: 2022-01-07 11:11:01 - * @FilePath: /rt-thread/bsp/hc32l073/board/board_config.h + * @LastEditTime: 2022-01-10 20:03:16 + * @FilePath: /motion_ec_rtt/board/board_config.h */ /* * @@ -44,4 +44,49 @@ #define UART1_TX_AF GpioAf1 #endif + +// #if defined(BSP_USING_UART2) +// #define UART2_RX_PORT GpioPortA +// #define UART2_RX_PIN GpioPin3 +// #define UART2_RX_AF GpioAf1 + +// #define UART2_TX_PORT GpioPortA +// #define UART2_TX_PIN GpioPin2 +// #define UART2_TX_AF GpioAf1 +// #endif + + +// #if defined(BSP_USING_UART3) +// #define UART3_RX_PORT GpioPortA +// #define UART3_RX_PIN GpioPin3 +// #define UART3_RX_AF GpioAf1 + +// #define UART3_TX_PORT GpioPortA +// #define UART3_TX_PIN GpioPin2 +// #define UART3_TX_AF GpioAf1 +// #endif + + +#if defined(BSP_USING_LPUART0) + #define LPUART0_RX_PORT GpioPortC + #define LPUART0_RX_PIN GpioPin11 + #define LPUART0_RX_AF GpioAf2 + + #define LPUART0_TX_PORT GpioPortC + #define LPUART0_TX_PIN GpioPin10 + #define LPUART0_TX_AF GpioAf2 +#endif + + +// #if defined(BSP_USING_LPUART1) +// #define LPUART1_RX_PORT GpioPortA +// #define LPUART1_RX_PIN GpioPin3 +// #define LPUART1_RX_AF GpioAf1 + +// #define LPUART1_TX_PORT GpioPortA +// #define LPUART1_TX_PIN GpioPin2 +// #define LPUART1_TX_AF GpioAf1 +// #endif + + #endif diff --git a/drivers/drv_usart.c b/drivers/drv_usart.c new file mode 100644 index 0000000..58018b3 --- /dev/null +++ b/drivers/drv_usart.c @@ -0,0 +1,312 @@ +/* + * @Description: + * @Date: 2022-01-10 17:36:06 + * @LastEditors: CK.Zh + * @LastEditTime: 2022-01-10 19:53:36 + * @FilePath: /motion_ec_rtt/drivers/drv_usart.c + */ +/* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-9-1 DongBowen first version + */ + +#include "drv_usart.h" +#include +#include +#include "board.h" + +#ifdef RT_USING_SERIAL +#ifdef BSP_USING_UART + +#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && \ + !defined(BSP_USING_UART3) + #error "Please define at least one BSP_USING_UARTx" + /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ +#endif + +enum +{ +#ifdef BSP_USING_UART0 + UART0_INDEX, +#endif +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif +#ifdef BSP_USING_UART3 + UART3_INDEX, +#endif +}; + +static struct hc_uart_cfg uart_cfg[] = +{ +#ifdef BSP_USING_UART0 + UART0_CFG, +#endif +#ifdef BSP_USING_UART1 + UART1_CFG, +#endif +#ifdef BSP_USING_UART2 + UART2_CFG, +#endif +#ifdef BSP_USING_UART3 + UART3_CFG, +#endif +#ifdef BSP_USING_LPUART0 + LPUART0_CFG, +#endif +#ifdef BSP_USING_LPUART1 + LPUART1_CFG, +#endif +}; + +static struct hc_uart uart_drv[sizeof(uart_cfg) / sizeof(uart_cfg[0])] = {0}; + +static rt_err_t _uart_init(struct rt_serial_device *serial_device, struct serial_configure *configure) +{ + stc_gpio_cfg_t stcGpioCfg; + stc_uart_cfg_t stcCfg; + + struct hc_uart_cfg *cfg; + RT_ASSERT(serial_device != RT_NULL); + RT_ASSERT(configure != RT_NULL); + cfg = serial_device->parent.user_data; + + /* configure rx and tx gpio */ + rt_memset(&stcGpioCfg, 0, sizeof(stcGpioCfg)); + Sysctrl_SetPeripheralGate(SysctrlPeripheralGpio, TRUE); + stcGpioCfg.enDir = GpioDirOut; + Gpio_Init(cfg->tx_port, cfg->tx_pin, &stcGpioCfg); + Gpio_SetAfMode(cfg->tx_port, cfg->tx_pin, cfg->tx_af); + stcGpioCfg.enDir = GpioDirIn; + Gpio_Init(cfg->rx_port, cfg->rx_pin, &stcGpioCfg); + Gpio_SetAfMode(cfg->rx_port, cfg->rx_pin, cfg->rx_af); + + /* configure uart */ + rt_memset(&stcCfg, 0, sizeof(stcCfg)); + + Sysctrl_SetPeripheralGate(cfg->uart_periph, TRUE); + + stcCfg.stcBaud.u32Baud = configure->baud_rate; + stcCfg.stcBaud.enClkDiv = UartMsk8Or16Div; + stcCfg.stcBaud.u32Pclk = Sysctrl_GetPClkFreq(); + + switch (configure->data_bits) + { + case DATA_BITS_8: + break; + default: + break; + } + + switch (configure->stop_bits) + { + case STOP_BITS_1: + stcCfg.enStopBit = UartMsk1bit; + break; + case STOP_BITS_2: + stcCfg.enStopBit = UartMsk2bit; + break; + default: + stcCfg.enStopBit = UartMsk1bit; + break; + } + + switch (configure->parity) + { + case PARITY_NONE: + stcCfg.enMmdorCk = UartMskDataOrAddr; + stcCfg.enRunMode = UartMskMode1; + break; + case PARITY_ODD: + stcCfg.enMmdorCk = UartMskOdd; + stcCfg.enRunMode = UartMskMode3; + break; + case PARITY_EVEN: + stcCfg.enMmdorCk = UartMskEven; + stcCfg.enRunMode = UartMskMode3; + break; + default: + stcCfg.enMmdorCk = UartMskDataOrAddr; + stcCfg.enRunMode = UartMskMode1; + break; + } + + Uart_Init(cfg->uart, &stcCfg); + + Uart_ClrStatus(cfg->uart, UartRC); + Uart_ClrStatus(cfg->uart, UartTC); + + rt_hw_us_delay(2); + return RT_EOK; +} + +static rt_err_t _uart_control(struct rt_serial_device *serial_device, int cmd, void *arg) +{ + struct hc_uart_cfg *cfg; + RT_ASSERT(serial_device != RT_NULL); + cfg = serial_device->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + Uart_DisableIrq(cfg->uart, UartRxIrq); + EnableNvic(cfg->irqn, IrqLevel3, FALSE); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + Uart_EnableIrq(cfg->uart, UartRxIrq); + EnableNvic(cfg->irqn, IrqLevel3, TRUE); + break; + } + return RT_EOK; +} + +static int _uart_putc(struct rt_serial_device *serial_device, char c) +{ + struct hc_uart_cfg *cfg; + RT_ASSERT(serial_device != RT_NULL); + cfg = serial_device->parent.user_data; + + Uart_SendDataPoll(cfg->uart, (uint8_t)c); + return 1; +} + +static int _uart_getc(struct rt_serial_device *serial_device) +{ + int ch; + struct hc_uart_cfg *cfg; + RT_ASSERT(serial_device != RT_NULL); + cfg = serial_device->parent.user_data; + + ch = -1; + + if (Uart_GetStatus(cfg->uart, UartRC)) + { + Uart_ClrStatus(cfg->uart, UartRC); + ch = Uart_ReceiveData(cfg->uart); + } + + return ch; +} + +static const struct rt_uart_ops _uart_ops = +{ + .configure = _uart_init, + .control = _uart_control, + .putc = _uart_putc, + .getc = _uart_getc, + .dma_transmit = RT_NULL +}; + +/** + * Uart common interrupt process. This need add to uart ISR. + * + * @param serial serial device + */ +static void rt_hw_uart_isr(struct rt_serial_device *serial_device) +{ + struct hc_uart_cfg *cfg; + uint32_t status; + RT_ASSERT(serial_device != RT_NULL); + + cfg = serial_device->parent.user_data; + status = cfg->uart->ISR; + + /* UART in mode Receiver -------------------------------------------------*/ + if (status & (1 << UartFE)) + { + Uart_ClrStatus(cfg->uart, UartFE); + } + if (status & (1 << UartPE)) + { + Uart_ClrStatus(cfg->uart, UartPE); + } + if (status & (1 << UartRC)) + { + rt_hw_serial_isr(serial_device, RT_SERIAL_EVENT_RX_IND); + } +} + +#if defined(BSP_USING_UART0) +void Uart0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_hw_uart_isr(&(uart_drv[UART0_INDEX].serial_device)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART0 */ + +#if defined(BSP_USING_UART1) +void Uart1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_hw_uart_isr(&(uart_drv[UART1_INDEX].serial_device)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +void Uart2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_hw_uart_isr(&(uart_drv[UART2_INDEX].serial_device)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +void Uart3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_hw_uart_isr(&(uart_drv[UART3_INDEX].serial_device)); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART3 */ + +int rt_hw_uart_init(void) +{ + struct serial_configure cfg = RT_SERIAL_CONFIG_DEFAULT; + int i = 0; + rt_err_t result = RT_EOK; + + for (i = 0; i < sizeof(uart_cfg) / sizeof(uart_cfg[0]); i++) + { + uart_drv[i].cfg = &uart_cfg[i]; + uart_drv[i].serial_device.ops = &_uart_ops; + uart_drv[i].serial_device.config = cfg; + /* register UART device */ + result = rt_hw_serial_register(&uart_drv[i].serial_device, uart_drv[i].cfg->name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart_drv[i].cfg); + RT_ASSERT(result == RT_EOK); + } + + return result; +} +INIT_BOARD_EXPORT(rt_hw_uart_init); + +#endif /* BSP_USING_UART */ +#endif /* RT_USING_SERIAL */ \ No newline at end of file diff --git a/drivers/drv_usart.h b/drivers/drv_usart.h new file mode 100644 index 0000000..edd3af4 --- /dev/null +++ b/drivers/drv_usart.h @@ -0,0 +1,161 @@ +/* + * @Description: + * @Date: 2022-01-10 17:36:12 + * @LastEditors: CK.Zh + * @LastEditTime: 2022-01-10 19:58:24 + * @FilePath: /motion_ec_rtt/drivers/drv_usart.h + */ +/* + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-9-1 DongBowen first version + */ + +#ifndef __DRV_USART_H__ +#define __DRV_USART_H__ + +#include +#include "rtdevice.h" + +#include "board_config.h" + +/* hc config class */ +struct hc_uart_cfg +{ + const char *name; + M0P_UART_TypeDef *uart; + en_sysctrl_peripheral_gate_t uart_periph; + IRQn_Type irqn; + + en_gpio_port_t rx_port; + en_gpio_pin_t rx_pin; + en_gpio_af_t rx_af; + + en_gpio_port_t tx_port; + en_gpio_pin_t tx_pin; + en_gpio_af_t tx_af; +}; + +/* hc uart dirver class */ +struct hc_uart +{ + struct hc_uart_cfg *cfg; + struct rt_serial_device serial_device; +}; + +#ifdef BSP_USING_UART0 +#ifndef UART0_CFG +#define UART0_CFG \ + { \ + .name = "uart0", \ + .uart = M0P_UART0, \ + .uart_periph = SysctrlPeripheralUart0, \ + .irqn = UART0_2_IRQn, \ + .rx_port = UART0_RX_PORT, \ + .rx_pin = UART0_RX_PIN, \ + .rx_af = UART0_RX_AF, \ + .tx_port = UART0_TX_PORT, \ + .tx_pin = UART0_TX_PIN, \ + .tx_af = UART0_TX_AF, \ + } +#endif /* UART0_CFG */ +#endif /* BSP_USING_UART0 */ + +#ifdef BSP_USING_UART1 +#ifndef UART1_CFG +#define UART1_CFG \ + { \ + .name = "uart1", \ + .uart = M0P_UART1, \ + .uart_periph = SysctrlPeripheralUart1, \ + .irqn = UART1_3_IRQn, \ + .rx_port = UART1_RX_PORT, \ + .rx_pin = UART1_RX_PIN, \ + .rx_af = UART1_RX_AF, \ + .tx_port = UART1_TX_PORT, \ + .tx_pin = UART1_TX_PIN, \ + .tx_af = UART1_TX_AF, \ + } +#endif /* UART1_CFG */ +#endif /* BSP_USING_UART1 */ + +#ifdef BSP_USING_UART2 +#ifndef UART2_CFG +#define UART2_CFG \ + { \ + .name = "uart2", \ + .uart = M0P_UART2, \ + .uart_periph = SysctrlPeripheralUart2, \ + .irqn = UART0_2_IRQn, \ + .rx_port = UART2_RX_PORT, \ + .rx_pin = UART2_RX_PIN, \ + .rx_af = UART2_RX_AF, \ + .tx_port = UART2_TX_PORT, \ + .tx_pin = UART2_TX_PIN, \ + .tx_af = UART2_TX_AF, \ + } +#endif /* UART2_CFG */ +#endif /* BSP_USING_UART2 */ + +#ifdef BSP_USING_UART3 +#ifndef UART3_CFG +#define UART3_CFG \ + { \ + .name = "uart3", \ + .uart = M0P_UART3, \ + .uart_periph = SysctrlPeripheralUart3, \ + .irqn = UART1_3_IRQn, \ + .rx_port = UART3_RX_PORT, \ + .rx_pin = UART3_RX_PIN, \ + .rx_af = UART3_RX_AF, \ + .tx_port = UART3_TX_PORT, \ + .tx_pin = UART3_TX_PIN, \ + .tx_af = UART3_TX_AF, \ + } +#endif /* UART3_CFG */ +#endif /* BSP_USING_UART3 */ + + +#ifdef BSP_USING_LPUART0 +#ifndef LPUART0_CFG +#define LPUART0_CFG \ + { \ + .name = "lpuart0", \ + .uart = M0P_LPUART0, \ + .uart_periph = SysctrlPeripheralLpUart0, \ + .irqn = LPUART0_IRQn, \ + .rx_port = LPUART0_RX_PORT, \ + .rx_pin = LPUART0_RX_PIN, \ + .rx_af = LPUART0_RX_AF, \ + .tx_port = LPUART0_TX_PORT, \ + .tx_pin = LPUART0_TX_PIN, \ + .tx_af = LPUART0_TX_AF, \ + } +#endif /* LPUART0_CFG */ +#endif /* BSP_USING_LPUART0 */ + + +#ifdef BSP_USING_LPUART1 +#ifndef LPUART1_CFG +#define LPUART1_CFG \ + { \ + .name = "lpuart1", \ + .uart = M0P_LPUART1, \ + .uart_periph = SysctrlPeripheralLpUart1, \ + .irqn = LPUART1_IRQn, \ + .rx_port = LPUART1_RX_PORT, \ + .rx_pin = LPUART1_RX_PIN, \ + .rx_af = LPUART1_RX_AF, \ + .tx_port = LPUART1_TX_PORT, \ + .tx_pin = LPUART1_TX_PIN, \ + .tx_af = LPUART1_TX_AF, \ + } +#endif /* LPUART1_CFG */ +#endif /* BSP_USING_LPUART1 */ + +int rt_hw_uart_init(void); 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z2mi|du{{0vGm_uxx9|PBMXCRUDF!rj&G6sppI2~8CSv97dp9TgQt(A$j*G?*T_(5L z0sX&|a{Z6LPs%;6BXXS-oBXx%mcF)De)651q41e8!IXoQv-HebdHa8%Gr5#MTq{2_ zkwk9Zit@zE$n1CD$CkAI_fzYp*Ua>m@96jKM6texTlxBL*o|8`m71yyepBl|OcM+) w`u_oMKp|_l`5!WGlbz`7dgWo^dgJ+qNNV*OdKPY0D}V4YDStt&KrQS32i!;%{Qv*} literal 0 HcmV?d00001 diff --git a/rtconfig.h b/rtconfig.h index d2067d9..f8356bf 100644 --- a/rtconfig.h +++ b/rtconfig.h @@ -1,10 +1,3 @@ -/* - * @Description: - * @Date: 2022-01-06 14:31:32 - * @LastEditors: CK.Zh - * @LastEditTime: 2022-01-10 16:02:30 - * @FilePath: /rt-thread/bsp/hc32l073/rtconfig.h - */ #ifndef RT_CONFIG_H__ #define RT_CONFIG_H__ @@ -20,7 +13,6 @@ #define RT_TICK_PER_SECOND 1000 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK -#define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 256 @@ -44,7 +36,6 @@ #define RT_USING_MEMPOOL #define RT_USING_SMALL_MEM -#define RT_USING_SMALL_MEM_AS_HEAP #define RT_USING_HEAP /* Kernel Device Object */ @@ -52,8 +43,8 @@ #define RT_USING_DEVICE #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart1" -#define RT_VER_NUM 0x40100 +#define RT_CONSOLE_DEVICE_NAME "lpuart0" +#define RT_VER_NUM 0x40005 /* RT-Thread Components */ @@ -87,8 +78,9 @@ /* Device Drivers */ #define RT_USING_DEVICE_IPC -// #define RT_USING_SERIAL -// #define RT_USING_SERIAL_V1 +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN @@ -97,16 +89,10 @@ /* POSIX layer and C standard library */ +#define RT_USING_LIBC +#define RT_LIBC_USING_TIME #define RT_LIBC_DEFAULT_TIMEZONE 8 -/* POSIX (Portable Operating System Interface) layer */ - - -/* Interprocess Communication (IPC) */ - - -/* Socket is in the 'Network' category */ - /* Network */ /* Socket abstraction layer */ @@ -126,9 +112,19 @@ /* Utilities */ +#define RT_USING_ULOG +#define ULOG_OUTPUT_LVL_D +#define ULOG_OUTPUT_LVL 7 +#define ULOG_ASSERT_ENABLE +#define ULOG_LINE_BUF_SIZE 128 -/* RT-Thread Utestcases */ +/* log format */ +#define ULOG_USING_COLOR +#define ULOG_OUTPUT_TIME +#define ULOG_OUTPUT_LEVEL +#define ULOG_OUTPUT_TAG +#define ULOG_BACKEND_USING_CONSOLE /* RT-Thread online packages */ @@ -187,6 +183,8 @@ #define PKG_EASYLOGGER_NEWLINE_SIGN_CRLF #define PKG_EASYLOGGER_ENABLE_COLOR #define PKG_USING_EASYLOGGER_V200 +#define PKG_USING_ULOG_EASYFLASH +#define PKG_USING_ULOG_EASYFLASH_V00200 /* system packages */ @@ -201,6 +199,12 @@ /* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ +#define PKG_USING_CMSIS_5 +#define PKG_CMSIS_CORE +#define PKG_USING_CMSIS_5_LATEST_VERSION +#define PKG_USING_CMSIS_5_AUX +#define PKG_USING_CMSIS_RTOS2 +#define PKG_USING_CMSIS_RTOS2_LATEST_VERSION /* Micrium: Micrium software products porting for RT-Thread */ @@ -228,6 +232,9 @@ /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_USING_LPUART0 /* Board extended module Drivers */