302 lines
8.2 KiB
ArmAsm
302 lines
8.2 KiB
ArmAsm
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;/*
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; * Copyright (c) 2006-2018, RT-Thread Development Team
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; *
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; * SPDX-License-Identifier: Apache-2.0
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; *
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; * Change Logs:
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; * Date Author Notes
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; * 2011-08-14 weety first version
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; * 2015-04-15 ArdaFu Split from AT91SAM9260 BSP
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; * 2015-04-21 ArdaFu Remove remap code. Using mmu to map vector table
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; * 2015-06-04 aozima Align stack address to 8 byte.
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; */
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UND_STK_SIZE EQU 512
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SVC_STK_SIZE EQU 4096
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ABT_STK_SIZE EQU 512
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IRQ_STK_SIZE EQU 1024
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FIQ_STK_SIZE EQU 1024
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SYS_STK_SIZE EQU 512
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Heap_Size EQU 512
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S_FRAME_SIZE EQU (18*4) ;72
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S_PC EQU (15*4) ;R15
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MODE_USR EQU 0X10
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MODE_FIQ EQU 0X11
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MODE_IRQ EQU 0X12
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MODE_SVC EQU 0X13
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MODE_ABT EQU 0X17
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MODE_UND EQU 0X1B
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MODE_SYS EQU 0X1F
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MODEMASK EQU 0X1F
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NOINT EQU 0xC0
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;----------------------- Stack and Heap Definitions ----------------------------
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem
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SPACE UND_STK_SIZE
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EXPORT UND_STACK_START
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UND_STACK_START
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ALIGN 8
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SPACE ABT_STK_SIZE
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EXPORT ABT_STACK_START
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ABT_STACK_START
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ALIGN 8
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SPACE FIQ_STK_SIZE
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EXPORT FIQ_STACK_START
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FIQ_STACK_START
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ALIGN 8
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SPACE IRQ_STK_SIZE
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EXPORT IRQ_STACK_START
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IRQ_STACK_START
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ALIGN 8
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SPACE SYS_STK_SIZE
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EXPORT SYS_STACK_START
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SYS_STACK_START
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ALIGN 8
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SPACE SVC_STK_SIZE
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EXPORT SVC_STACK_START
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SVC_STACK_START
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Stack_Top
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__initial_sp
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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;--------------Jump vector table------------------------------------------------
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EXPORT Entry_Point
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AREA RESET, CODE, READONLY
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ARM
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Entry_Point
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LDR PC, vector_reset
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LDR PC, vector_undef
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LDR PC, vector_swi
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LDR PC, vector_pabt
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LDR PC, vector_dabt
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LDR PC, vector_resv
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LDR PC, vector_irq
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LDR PC, vector_fiq
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vector_reset
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DCD Reset_Handler
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vector_undef
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DCD Undef_Handler
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vector_swi
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DCD SWI_Handler
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vector_pabt
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DCD PAbt_Handler
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vector_dabt
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DCD DAbt_Handler
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vector_resv
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DCD Resv_Handler
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vector_irq
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DCD IRQ_Handler
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vector_fiq
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DCD FIQ_Handler
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;----------------- Reset Handler -----------------------------------------------
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IMPORT rt_low_level_init
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IMPORT __main
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EXPORT Reset_Handler
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Reset_Handler
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; set the cpu to SVC32 mode
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MRS R0,CPSR
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BIC R0,R0,#MODEMASK
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ORR R0,R0,#MODE_SVC:OR:NOINT
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MSR CPSR_cxsf,R0
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; Set CO-Processor
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; little-end，disbale I/D Cache MMU, vector table is 0x00000000
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MRC p15, 0, R0, c1, c0, 0 ; Read CP15
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LDR R1, =0x00003085 ; set clear bits
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BIC R0, R0, R1
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MCR p15, 0, R0, c1, c0, 0 ; Write CP15
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; Call low level init function,
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; disable and clear all IRQs, Init MMU, Init interrupt controller, etc.
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LDR SP, =SVC_STACK_START
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LDR R0, =rt_low_level_init
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BLX R0
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Setup_Stack
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; Setup Stack for each mode
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MRS R0, CPSR
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BIC R0, R0, #MODEMASK
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ORR R1, R0, #MODE_UND:OR:NOINT
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MSR CPSR_cxsf, R1 ; Undef mode
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LDR SP, =UND_STACK_START
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ORR R1,R0,#MODE_ABT:OR:NOINT
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MSR CPSR_cxsf,R1 ; Abort mode
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LDR SP, =ABT_STACK_START
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ORR R1,R0,#MODE_IRQ:OR:NOINT
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MSR CPSR_cxsf,R1 ; IRQ mode
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LDR SP, =IRQ_STACK_START
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ORR R1,R0,#MODE_FIQ:OR:NOINT
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MSR CPSR_cxsf,R1 ; FIQ mode
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LDR SP, =FIQ_STACK_START
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ORR R1,R0,#MODE_SYS:OR:NOINT
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MSR CPSR_cxsf,R1 ; SYS/User mode
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LDR SP, =SYS_STACK_START
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ORR R1,R0,#MODE_SVC:OR:NOINT
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MSR CPSR_cxsf,R1 ; SVC mode
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LDR SP, =SVC_STACK_START
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; Enter the C code
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LDR R0, =__main
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BLX R0
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;----------------- Exception Handler -------------------------------------------
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IMPORT rt_hw_trap_udef
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IMPORT rt_hw_trap_swi
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IMPORT rt_hw_trap_pabt
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IMPORT rt_hw_trap_dabt
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IMPORT rt_hw_trap_resv
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IMPORT rt_hw_trap_irq
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IMPORT rt_hw_trap_fiq
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IMPORT rt_interrupt_enter
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IMPORT rt_interrupt_leave
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IMPORT rt_thread_switch_interrupt_flag
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IMPORT rt_interrupt_from_thread
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IMPORT rt_interrupt_to_thread
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Undef_Handler PROC
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SUB SP, SP, #S_FRAME_SIZE
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STMIA SP, {R0 - R12} ; Calling R0-R12
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ADD R8, SP, #S_PC
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STMDB R8, {SP, LR} ; Calling SP, LR
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STR LR, [R8, #0] ; Save calling PC
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MRS R6, SPSR
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STR R6, [R8, #4] ; Save CPSR
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STR R0, [R8, #8] ; Save SPSR
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MOV R0, SP
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BL rt_hw_trap_udef
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ENDP
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SWI_Handler PROC
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BL rt_hw_trap_swi
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ENDP
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PAbt_Handler PROC
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BL rt_hw_trap_pabt
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ENDP
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DAbt_Handler PROC
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SUB SP, SP, #S_FRAME_SIZE
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STMIA SP, {R0 - R12} ; Calling R0-R12
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ADD R8, SP, #S_PC
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STMDB R8, {SP, LR} ; Calling SP, LR
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STR LR, [R8, #0] ; Save calling PC
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MRS R6, SPSR
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STR R6, [R8, #4] ; Save CPSR
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STR R0, [R8, #8] ; Save SPSR
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MOV R0, SP
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BL rt_hw_trap_dabt
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ENDP
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Resv_Handler PROC
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BL rt_hw_trap_resv
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ENDP
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FIQ_Handler PROC
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STMFD SP!, {R0-R7,LR}
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BL rt_hw_trap_fiq
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LDMFD SP!, {R0-R7,LR}
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SUBS PC, LR, #4
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ENDP
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IRQ_Handler PROC
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STMFD SP!, {R0-R12,LR}
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BL rt_interrupt_enter
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BL rt_hw_trap_irq
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BL rt_interrupt_leave
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; If rt_thread_switch_interrupt_flag set,
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; jump to rt_hw_context_switch_interrupt_do and don't return
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LDR R0, =rt_thread_switch_interrupt_flag
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LDR R1, [R0]
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CMP R1, #1
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BEQ rt_hw_context_switch_interrupt_do
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LDMFD SP!, {R0-R12,LR}
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SUBS PC, LR, #4
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ENDP
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;------ void rt_hw_context_switch_interrupt_do(rt_base_t flag) -----------------
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rt_hw_context_switch_interrupt_do PROC
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MOV R1, #0 ; Clear flag
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STR R1, [R0] ; Save to flag variable
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LDMFD SP!, {R0-R12,LR} ; Reload saved registers
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STMFD SP, {R0-R2} ; Save R0-R2
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SUB R1, SP, #4*3 ; Save old task's SP to R1
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SUB R2, LR, #4 ; Save old task's PC to R2
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MRS R0, SPSR ; Get CPSR of interrupt thread
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MSR CPSR_c, #MODE_SVC:OR:NOINT ; Switch to SVC mode and no interrupt
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STMFD SP!, {R2} ; Push old task's PC
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STMFD SP!, {R3-R12,LR} ; Push old task's LR,R12-R3
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LDMFD R1, {R1-R3}
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STMFD SP!, {R1-R3} ; Push old task's R2-R0
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STMFD SP!, {R0} ; Push old task's CPSR
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LDR R4, =rt_interrupt_from_thread
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LDR R5, [R4] ; R5 = stack ptr in old tasks's TCB
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STR SP, [R5] ; Store SP in preempted tasks's TCB
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LDR R6, =rt_interrupt_to_thread
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LDR R6, [R6] ; R6 = stack ptr in new tasks's TCB
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LDR SP, [R6] ; Get new task's stack pointer
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LDMFD SP!, {R4} ; Pop new task's SPSR
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MSR SPSR_cxsf, R4
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LDMFD SP!, {R0-R12,LR,PC}^ ; pop new task's R0-R12,LR & PC SPSR to CPSR
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ENDP
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;*******************************************************************************
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; User Stack and Heap initialization
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;*******************************************************************************
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap
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LDR R0, = Heap_Mem ; heap base
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LDR R1, = SVC_STACK_START ; stack base (top-address)
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LDR R2, = (Heap_Mem + Heap_Size) ; heap limit
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LDR R3, = (SVC_STACK_START - SVC_STK_SIZE) ; stack limit (low-address)
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BX LR
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ALIGN
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ENDIF
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END
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